
SCSI Functional Description
2-33
This is necessary since the next instruction to be executed is not the
sequential next instruction in the prefetch unit.
When the Prefetch Flush bit (
DMA Control (DCNTL)
register, bit 6)
is set
The unit flushes whenever this bit is set. This bit is self-clearing.
2.2.7 Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit (bit 1) in the
DMA Mode
(DMODE)
register (0x38) causes the SYM53C1010 to burst in the first
two Dwords of all instruction fetches. If the instruction is a Memory-to-
Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Table Indirect Block
Move, the device uses two accesses, each a two Dword burst, to obtain
the four Dwords required.
Note:
This feature is only useful if Prefetching is disabled.
This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, burst opcode fetching is not necessary
when fetching instructions from SCRIPTS RAM.
2.2.8 Load and Store Instructions
The SYM53C1010 supports the Load and Store instruction type, which
simplifies data movement between memory and the internal registers. It
also enables the chip to transfer bytes to addresses relative to the
Data
Structure Address (DSA)
register. Load and Store data transfers to or
from the SCRIPTS RAM remain internal to the chip and do not generate
PCI bus cycles. While a Load/Store to or from SCRIPTS RAM is
occurring, any external PCI slave cycles that occur are retried on the PCI
bus. Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit in
the
Chip Control Zero (CCNTL0)
register disables this feature. For more
information on the Load and Store instructions, refer to
Chapter 5, “SCSI
SCRIPTS Instruction Set”
.