![](http://datasheet.mmic.net.cn/390000/SYM53C1010-33_datasheet_16836324/SYM53C1010-33_47.png)
SCSI Functional Description
2-19
2.1.4.6 Memory-to-Memory Moves
Memory-to-Memory moves also support PCI cache commands, as
described above, with one limitation: Memory Write and Invalidate on
Memory-to-Memory move writes are only supported if the source and
destination address are quad word aligned. If the source and destination
are not quad word aligned, i.e., Source Address[2:0] == Destination
Address[2:0], write alignment is not performed and Memory Write and
Invalidates are not issued.
The SYM53C1010 is little endian. This mode assigns the least significant
byte to bits [7:0].
2.2 SCSI Functional Description
Both Ultra3 SCSI controllers on the SYM53C1010 provide a SCSI
function that supports either an 8-bit or 16-bit bus. Each controller
supports Wide Ultra3 SCSI synchronous transfer rates up to 160
Mbytes/s on a LVD SCSI bus. SCSI functions can be programmed with
SCSI SCRIPTS, making it easy to “fine tune” the system for specific
mass storage devices or Ultra3 SCSI requirements.
Figure 2.1
illustrates
the relationship between the SYM53C1010 modules.
The SYM53C1010 offers low level register access or a high level control
interface. Like first generation SCSI devices, the SYM53C1010 is
accessed as a register-oriented device. The ability to sample and/or
assert any signal on the SCSI bus is used in error recovery and
diagnostic procedures.
The SYM53C1010 is controlled by the integrated SCRIPTS processor
through a high level logical interface. Commands controlling the SCSI
functions are fetched out of the main host memory or local memory.
These commands instruct the SCSI functions to Select, Reselect,
Disconnect, Wait for a Disconnect, Transfer Information, Change Bus
Phases, and implement all other aspects of the SCSI protocol. The
SCRIPTS processor is a special high speed processor optimized for
SCSI protocol.