![](http://datasheet.mmic.net.cn/390000/SYM53C1010-33_datasheet_16836324/SYM53C1010-33_58.png)
2-30
Functional Description
The
CRC Control Zero (CRCCNTL0)
register:
–
Bit 7, DISCRCCK (Disable CRC Checking), is set to cause the
internal logic to not check or report CRC errors during Ultra3
transfers. The device continues to calculate and send CRC’s as
requested by the target per SPI-3 specification.
–
Bit 6, DISCRC (Disable CRC protocol checking) causes the
SYM53C1010 to not check for a CRC request prior to a phase
change on the SCSI bus. This condition creates a SCSI error
condition and makes the device noncompliant with the SPI-3
specification. This bit should not be set under normal operating
conditions.
–
Bit 5, RSTCRCINT (Reset CRC Interval Counter) resets the
internal CRC interval counter to zero.
–
Bit 4 is reserved.
–
Bits [3:0], CRCINT[3:0] (CRC Request Interval (Target Mode
only)), determine when a CRC request is sent by the device
when operating in target mode and transferring data in DT Data-
In or DT Data-Out Phases.
The
CRC Control One (CRCCNTL1)
register:
–
Bit 7, CRCERR (CRC Error), indicates whether or not a CRC
error has been detected during a DT Data-In SCSI transfer. This
bit is independent of the DISCRCCHK bit setting. To clear this
condition, either write this bit to a one or read the
SCSI Interrupt
Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
registers. When CRC checking and the Parity/CRC/AIP Error
interrupt are both enabled, CRCERR is mirrored in the SIST0
register, bit 0, as a Parity/CRC/AIP error.
–
Bit 6 is reserved.
–
Bit 5, ENAS (Enable CRC Auto Seed), is set to cause the CRC
logic to automatically reseed itself after every CRC check
performed during DT Data-In SCSI transfers. When this bit is
cleared, the SCSI control logic controls when the CRC logic is
reseeded.
–
Bit 4, TSTSD (Test CRC Seed), is set to cause the CRC logic to
immediately reseed itself. This bit should never be set during
normal operation as it may cause corrupt CRCs to be generated.