![](http://datasheet.mmic.net.cn/390000/SYM53C1010-33_datasheet_16836324/SYM53C1010-33_374.png)
IX-8
Index
address - A[6:0]
5-23
register map
A-1
,
A-2
registers
2-48
relative
5-20
relative addressing mode
5-19
,
5-30
remaining byte count (RBC)
4-113
REQ/
2-10
,
3-12
REQ/ - GNT/
2-2
REQ64/
3-11
request
3-12
request 64
3-11
reselect
2-19
during reselection
2-42
instruction
5-15
reselected (RSL)
4-72
,
4-76
reserved command
2-6
reset
3-9
input
6-12
SCSI offset (ROF)
4-88
response ID one (RESPID1)
4-84
response ID zero (RESPID0)
4-84
return instruction
5-28
revision ID register
(RID[7:0])
4-7
rise and fall time test condition
6-8
ROM
flash and memory interface signals
3-23
RST/
3-9
S
SACK
2-53
SACs
2-22
scan mode
3-24
SCAN_MODE
3-24
SCLK
3-17
quadrupler enable (QEN)
4-86
quadrupler select (QSEL)
4-86
scratch
byte register (SBR)
4-68
register A (SCRATCHA)
4-64
,
4-123
register B (SCRATCHB)
4-98
,
4-125
registers C–R (SCRATCHC–SCRATCHR)
4-99
,
4-125
script fetch selector (SFS)
4-100
,
4-126
SCRIPTS
interrupt instruction received (SIR)
4-41
,
4-67
processor
2-20
internal RAM for instruction storage
2-20
performance
2-20
RAM
2-4
,
2-20
running (SRUN)
4-51
SCSI
ATN condition - target mode (M/A)
4-71
bus control lines (SBCL)
4-40
bus data lines (SBDL)
4-96
bus interface
2-40
bus mode change (SBMC)
4-74
,
4-78
bus modes
2-41
byte count (SBC)
4-116
C_D/ signal (C_D)
4-45
chip ID (SCID)
4-33
clock
3-17
control enable (SCE)
4-87
control four (SCNTL4)
2-44
control one (SCNTL1)
2-36
,
4-28
control three (SCNTL3)
2-43
,
4-32
control two (SCNTL2)
4-30
control zero (SCNTL0)
2-36
,
4-24
cumulative byte count
4-117
destination ID (SDID)
4-35
disconnect unexpected (SDU)
4-30
encoded destination ID
5-21
first byte received (SFBR)
4-37
function A control
3-19
function A GPIO signals
3-15
function A signals
3-17
function B control
3-22
function B GPIO signals
3-16
function B signals
3-20
functional description
2-19
gross error (SGE)
4-72
,
4-76
hysteresis of receivers
6-9
I_O/ signal (I_O)
4-45
input data latch (SIDL)
4-90
input filtering
6-8
instructions
block move
5-5
I/O
5-15
read/write
5-23
interface signals
3-17
interrupt enable one (SIEN1)
2-50
,
4-73
interrupt enable zero (SIEN0)
2-36
,
2-50
,
4-71
interrupt pending (SIP)
4-50
interrupt status one (SIST1)
2-49
,
2-50
,
2-52
,
2-54
,
4-78
,
4-
124
interrupt status zero (SIST0)
2-36
,
2-49
,
2-50
,
2-52
,
2-54
,
4-
75
interrupts
2-53
low level mode (LOW)
4-88
LVD Link
2-41
mode (SMODE[1:0])
4-91
MSG/ signal (MSG)
4-45
output control latch (SOCL)
4-38
output data latch (SODL)
4-92
parity/CRC error (PAR)
4-73
performance
1-7
phase
5-13
,
5-29
phase mismatch - initiator mode
4-71
registers
4-22
reset condition (RST)
4-73
RST/ received (RST)
4-77
RST/ signal (RST)
4-44
SCRIPTS operation
5-1
sample instruction
5-3
SDP0/ parity signal (SDP0)
4-44
SDP1/ parity signal (SDP1)
4-47
selected as ID (SSAID[3:0])
4-85
selector ID (SSID)
4-39
status one (SSTAT1)
2-36
,
4-45
status two (SSTAT2)
2-36
,
4-46
status zero (SSTAT0)
2-36
,
4-43
synchronous offset maximum (SOM)
4-86
synchronous offset zero (SOZ)
4-85
termination
2-41
test four (STEST4)
4-91
test one (STEST1)
4-86
test three (STEST3)
4-89
test two (STEST2)
4-87
test zero (STEST0)
4-85
timer one (STIME1)
4-82
timer zero (STIME0)
4-81
timing diagrams
6-58