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參數(shù)資料
| 型號： | SME1430LGA-480 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封裝： | CERAMIC, LGA-587 |
| 文件頁數(shù)： | 7/60頁 |
| 文件大?。?/td> | 646K |
| 代理商： | SME1430LGA-480 |
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15
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
May 1999
Sun Microsystems, Inc
Internal, SRAM, and UPA Clock Interface
Symbol
Volts
Type
Signal
Transitions
Aligned with:
Name and Function
CLKA
LVPECL
I
See
and
Figure 4 for
logical relation
of clocks
Primary positive differential clock source to
the UltraSPARC-II
i CPU; normally (in 2X mode) runs at 1/2 the
internal clock rate; during test, when the PLL is bypassed, the full
internal clock rate can be used
CLKB
I
Primary negative differential clock source to
the UltraSPARC-IIi
CPU; normally (in 2X mode) runs at 1/2 the internal clock rate;
during test, when the PLL is bypassed, the full internal clock rate
can be used
UPA_CLK_POS,
UPA_CLK_NEG
I
Signals run at 1/4 frequency of the internal CPU clock; also used
to drive the UPA64S; when the UPA64S interface is used these
signals indicate to the processor which CLKA edge corresponds
to a UPA_CLK_POS edge
SRAM_CLK_POS
SRAM_CLK_NEG
I
Signals run at 1/2 the internal clock rate; also drive the SRAMs;
they indicate to the processor which CLKA edges correspond to
SRAM_CLK_POS clock edges
PLLBYPASS
3.3 V
I
Static Signal
Used during test to bypass PLL and PLL2; clock from differential
receiver is directly passed to the clock tree; during PLLBYPASS,
SRAM_CLK_POS and SRAM_CLK_NEG must be 1/2 the
frequency of CLKA and CLKB; also during PLLBYPASS,
UPA_CLK_POS and UPA_CLK_NEG must be 1/3 the frequency
of CLKA and CLKB; during PLLBYPASS mode, PCI_REF_CLK
must be 2X frequency of PCI_CLK
L5CLK
1.9 V
O
CLKA and CLKB
Internal level 5 clock that reects the CPU clock; used to
determine PLL lock or clock tree delay when in PLL bypass mode;
may be disabled during normal operation
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