參數(shù)資料
型號: SME1430LGA-480
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587
封裝: CERAMIC, LGA-587
文件頁數(shù): 29/60頁
文件大?。?/td> 646K
代理商: SME1430LGA-480
35
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
May 1999
Sun Microsystems, Inc
Figure 16. Timing for L2-cache Writes with E-to-M State Transition (2-2-2 mode)
Figure 16 shows the timing of L2-cache writes with E-to-M state transition. The tag checks in clock cycles 2, 3
and 4 found the line in Exclusive (E) state. The tag is updated to Modied (M) state at the same time data is
written in clocks 5, 6, and 7 respectively.
SRAM CYCLE
012345
TSYN_WR_L
R0
R1
R2
TOE_L
R0
R1
R2
ECAT
A0_tag
TDATA
D0_tag
DSYN_WR_L
DOE_L
ECAD
EDATA
CPU CLK
SRAM CLK
6
7
8
W0
D0_data
A1_tag
A2_tag
A0_tag
A1_tag
A2_tag
D1_tag
D2_tag
D0_tag
D1_tag
D1_data
D2_data
W1
W2
W0
W1
W2
D2_tag
A0_data
A1_data
A2_data
W0
W1
W2
W0
W1
W2
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