
42
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
DC Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VOH
High-level
output voltage
1.9 V signals
VDDO = Min, IOH = Max
1.65
–
V
3.3 V non-PCI signals
VDDH = Min, IOH = Max
2.0
–
V
3.3 V PCI signals
Iout = -500
A
0.9VDDH
––
V
VOL
Low-level
output voltage
1.9 V signals
VDDO = Min, IOL = Max
–
1.15
V
3.3 V non-PCI signals
VDDH = Min, IOL = Max
–
0.8
V
3.3 V PCI signals
Iout = 1500
A
–
0.1VDDH
V
VIH
High-level input
voltage
1.9 V signals
VDDC = Max
1.65
–
V
LVPECL signals
VDDC = Max
VDDPLL-
0.345
––
V
HSTL signals
Vcm -
0.25
––
V
3.3 V non-PCI signals
VDDH = Max
2.0
–
V
3.3 V PCI signals
VDDH = Max
0.5VDDH
-
0.5 + VDDH V
VIL
Low-level input
voltage
1.9 V signals
VDDC = Min
–
1.15
V
LVPECL signals
VDDC = Min
–
VDDPLL
- 0.655
V
HSTL signals
–
Vcm + 0.25
V
3.3 V non-PCI signals
VDDH = Min
–
0.8
V
3.3 V PCI signals
VDDH = Min
-0.5
–
0.3VDDH
V
IDD(1.9V)
1.9 V Supply
current
360 MHz
VDDC, VDDO & VDDH =
max.
–
6.3
7.9
A
440 MHz
–
7.6
9.6
A
480 MHz
–
8.3
10.5
A
IDD(3.3V)
3.3V Supply
current
360 MHz
VDDC, VDDO & VDDH =
max.
–
0.55
0.65
A
440 MHz
–
0.6
0.7
A
480 MHz
–
0.65
0.75
A
IOZ
High-impedance output current [1]
(Outputs without pull-ups)
1. Only bidirectional lines can be tri-stated; output-only lines cannot be tri-stated. All bidirectional lines are tri-stated when SYS_RESET_L or
P_RESET_L is held LOW and RAM_TEST is held high.
VDD = max., VO = 2.4 V
–
20
pA
VDD = max., VO = 0.4 V
–
-20
pA
High-impedance output current
(Outputs with pull-ups)
VDD = max., VO = VSS to
VDD
–
250
pA
II
Input current (inputs without pull-ups)
VDD = max., VI = VSS to
VDD
-20
–
20
pA
Input current (inputs with pull-ups)
VDD = max., VI = VSS to
VDD
–
-250
pA
CI
Input capacitance [2]
2. This specication is provided as an aid to board design but is not assured during manufacturing testing.
––
5
–
pF
CO
Output capacitance
–
10
–
pF