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參數(shù)資料
| 型號： | SME1430LGA-480 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封裝： | CERAMIC, LGA-587 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 646K |
| 代理商： | SME1430LGA-480 |
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SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
Memory Model for Reference Platform
Figure 8. UltraSPARC-II
i Memory: Simplied Block Diagram
Figure 8 shows how memory is connected to, and controlled by, the UltraSPARC-IIi CPU. The memory
DIMMs are arranged on a 144-bit bus to allow an entire cache line to be fetched in four CAS accesses.
The UltraSPARC-IIi CPU implements ECC, with single-bit correction and multi-bit detection of errors, for all
memory data transfers.
PCI Buses for the UltraSPARC-IIi CPU and Advanced PCI Bridge
Figure 9 shows an example of the connection of an external PCI subsystem.
The interface from the UltraSPARC-IIi CPU with its I/O subsystems is a 32-bit PCI bus, which can run at
either 33 or 66 MHz. UltraSPARC-IIi internal PLLs allow slower PCI bus clock rates, down to 20 MHz or 40
MHz for each range respectively. This allows use of more PCI targets than the 2.1 specication permits for
full-speed operation. However, the PCI arbiters on SME1430LGA and APB only support four master requests.
The Advanced PCI Bridge (APB) allows external arbiters on the secondary buses.
The SME1430LGA PCI interface runs at 3.3 V only. To support 5 V PCI cards, the Advanced PCI Bridge (APB)
must be used, which also provides expansion from one 66 MHz 32-bit PCI bus, to two 32-bit 33 MHz PCI
buses. The APB provides up to 64-byte write posting and data prefetching, so that the delivered throughput
can be higher than a single 33 MHz bus could provide.
Memory Address
and Control
UltraSPARC-IIi
CPU
Up to 2 MB
L2 cache
Memory (8 DIMMs)
Transceivers
TA[16]
TD(16+2P)
DA(18+8BE)
D(64+8P)
Tag
SRAM
Data
(64+8ECC)
Memory Data
(128+16ECC)
Data
SRAMs
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