參數(shù)資料
型號(hào)： SME1430LGA-480
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587
封裝： CERAMIC, LGA-587
文件頁(yè)數(shù)： 25/60頁(yè)
文件大?。?/td> 646K
代理商： SME1430LGA-480
31
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
May 1999
Sun Microsystems, Inc
L2-cache Write Hit to M State Line in 2-2 Mode
Figure 12. Timing for L2-cache Write Hit to M State Line (2-2 mode)
Figure 12 shows the 2-2 timing mode for three consecutive write hits to the M state lines. Access to the rst tag
(D0_tag) is started by asserting TOE_L and by sending the tag address (A0_tag). In the cycle after the tag data
(D0_tag) comes back, the UltraSPARC-IIi CPU determines that the access is a hit and that the line is in Modi-
ed (M) state. In the next clock, a request is made to write the data. The data address is presented on the
ECAD pins in the cycle after the request (cycle 3 for W0) and the data is sent in the following cycle (cycle 4).
Systems running in 2-2 mode incur no read-to-write bus turnaround penalty.
SRAM CLK
SRAM CYCLE
0123456
TSYN_WR_L
R0
R1
R2
TOE_L
R0
R1
R2
ECAT
A0_tag
A1_tag
A2_tag
TDATA
D0_tag
D1_tag
D2_tag
DSYN_WR_L
DOE_L
W0
W1
W2
ECAD
A0_data
A1_data
A2_data
EDATA
D0_data
D1_data
D2_data
CPU CLK
W0
W1
W2
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