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參數(shù)資料
| 型號(hào)： | SME1430LGA-480 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封裝： | CERAMIC, LGA-587 |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 646K |
| 代理商： | SME1430LGA-480 |
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SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
Figure 9. Example of Externally-Connected PCI Subsystem
UPA64S interface (FFB)
UPA64S is a slave-only interface protocol used, for instance, by proprietary graphics boards. It can be used for
any high bandwidth control or data transfers between the processor and a dedicated subsystem.
The UltraSPARC-IIi CPU drives the SYSADR (system address), ADR_VLD (address valid) signals, the
S_REPLY control signals, and RST_L (reset) to the UPA64S. The data bus (64 bits out of 72) is shared with the
transceiver connection to the UltraSPARC-IIi CPU. The internal memory controller of the UltraSPARC-IIi
CPU transfers data in alignment with processor clocks, but guarantees that UPA64S transfers appear aligned
to the UPA64S clock. In other words, these are valid for four processor clock cycles, and only sampled on the
UPA clock edge when UPA64S is driving.
Note that, although the transceivers only cycle the 72-bit MEMDATA typically at 80 to 90 MHz , the
FFB/UPA64S interface cycles this bus at up to 120 MHz.
UltraSPARC-II
i
DRAM
Control
External
Cache Unit
PCI Subsystem
32 at 33 or 66MHz
3.3 v
L2-cache
72
2 FIFOs
Advanced PCI Bridge
FIFO
PCI
Agents
1, 2, . .. n
PCI
Agents
1, 2, . .. n
32 at 33 MHz
5 V Tolerant
Note: All FIFOs are 72 bytes
PCI
Agents
1, 2,. . . n
32 at 33 MHz
5 V Tolerant
TRANSCEIVERS
DIMMs
UPA64S
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| SME1701-BGA133 | 32-BIT, 133 MHz, MICROPROCESSOR, PBGA316 |
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| SME5410MCZ-270 | 64-BIT, 270 MHz, RISC PROCESSOR, XMA |
| SME5434PCI-440 | 64-BIT, 440 MHz, RISC PROCESSOR, XMA |
| SME5434PCI-480 | 64-BIT, 480 MHz, RISC PROCESSOR, XMA |
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