
50
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
MEM_DATA-0
AE27
MEM_DATA-1
AC25
MEM_DATA-2
AD26
MEM_DATA-3
AE28
MEM_DATA-4
AB25
MEM_DATA-5
AD27
MEM_DATA-6
AA23
MEM_DATA-7
AD28
MEM_DATA-8
AB26
MEM_DATA-9
AA24
MEM_DATA-10
AC28
MEM_DATA-11
AA26
MEM_DATA-12
AB27
MEM_DATA-13
Y24
MEM_DATA-14
AB28
MEM_DATA-15
AA27
MEM_DATA-16
Y25
MEM_DATA-17
W23
MEM_DATA-18
W24
MEM_DATA-19
Y26
MEM_DATA-20
Y27
MEM_DATA-21
V23
MEM_DATA-22
W26
MEM_DATA-23
W27
MEM_DATA-24
W28
MEM_DATA-25
V25
MEM_DATA-26
V26
MEM_DATA-27
V27
MEM_DATA-28
H27
MEM_DATA-29
J25
MEM_DATA-30
K23
MEM_DATA-31
G28
MEM_DATA-32
H26
MEM_DATA-33
J24
MEM_DATA-34
G27
MEM_DATA-35
F28
MEM_DATA-36
T27
MEM_DATA-37
R26
MEM_DATA-38
R23
MEM_DATA-39
R27
MEM_DATA-40
R28
MEM_DATA-41
P28
MEM_DATA-42
P23
MEM_DATA-43
P27
MEM_DATA-44
P26
MEM_DATA-45
P24
MEM_DATA-46
N25
MEM_DATA-47
N27
MEM_DATA-48
N26
MEM_DATA-49
M27
MEM_DATA-50
M24
MEM_DATA-51
M26
MEM_DATA-52
M25
MEM_DATA-53
L28
MEM_DATA-54
L25
MEM_DATA-55
L27
MEM_DATA-56
K28
MEM_DATA-57
L26
MEM_DATA-58
L23
MEM_DATA-59
K27
MEM_DATA-60
K26
MEM_DATA-61
J27
MEM_DATA-62
K24
MEM_DATA-63
J26
MEM_DATA-64
V28
MEM_DATA-65
U25
MEM_DATA-66
U24
MEM_DATA-67
U26
MEM_DATA-68
U27
MEM_DATA-69
T25
MEM_DATA-70
R24
MEM_DATA-71
T26
MEM_RASB_L-0
E27
MEM_RASB_L-1
H24
MEM_RASB_L-2
G25
MEM_RASB_L-3
G26
MEM_RAST_L-0
F25
MEM_RAST_L-1
H23
MEM_RAST_L-2
D28
MEM_RAST_L-3
E28
MEM_WE_L
C27
P2L5CLK
C02
PAR
L03
PCICLK
F05
PCI_REF_CLK
E03
PERR_L
K02
PLLBYPASS
M03
PMO
AC05
P_REPLY-0
E24
P_REPLY-1
G23
P_RESET_L
Y04
RAM_TEST
AE02
REQ_L-0
R02
REQ_L-1
R01
REQ_L-2
R05
REQ_L-3
P01
RMTV_SEL
AD25
RST_L
D02
SB_DRAIN
AA05
SB_EMPTY-0
AC01
SB_EMPTY-1
AD01
SERR_L
K01
SPARE3V
AB23
SRAM_CLK_NEG
M02
SRAM_CLK_POS
N02
STOP_L
K03
SYNC_3TO1_MODE
P03
SYSADR-0
B19
SYSADR-1
C19
SYSADR-2
C20
SYSADR-3
B21
SYSADR-4
A22
SYSADR-5
C21
SYSADR-6
B22
SYSADR-7
A23
SYSADR-8
A24
SYSADR-9
D22
SYSADR-10
B24
SYSADR-11
B25
SYSADR-12
D23
SYSADR-13
C25
SYSADR-14
B26
SYSADR-15
F18
SYSADR-16
B20
SYSADR-17
E19
SYSADR-18
D20
SYSADR-19
F19
SYSADR-20
E20
SYSADR-21
E21
SYSADR-22
C22
SYSADR-23
F21
SYSADR-24
A25
SYSADR-25
F22
SYSADR-26
C24
SYSADR-27
E23
SYSADR-28
D24
SYS_RESET_L
AA06
S_REPLY-0
F24
S_REPLY-1
E25
S_REPLY-2
D26
TCK
AB04
TDATA0
B02
TDATA-1
E06
TDATA-2
D05
TDATA-3
C04
TDATA-4
B03
TDATA-5
F07
TDATA-6
D06
TDATA-7
C05
TDATA-8
B04
TDATA-9
F08
TDATA-10
A04
TDATA-11
A05
TDATA-12
D07
TDATA-13
B05
TDATA-14
E08
TDATA-15
B07
TDI
AE01
TDO
AF02
TEMP_SEN-0
AE03
TEMP_SEN-1
AD04
TMS
AD02
TOE_L
C08
TPAR-0
A06
TPAR-1
C07
TRDY_L
K05
TRST_L
AC04
TSYN_WR_L
F10
UPA_CLK_NEG
M05
UPA_CLK_POS
M04
VDDC
F09
VDDC
F20
VDDC
G08
VDDC
G09
VDDC
G12
VDDC
G13
VDDC
G16
VDDC
G17
VDDC
G20
VDDC
G21
VDDC
H07
VDDC
H22
VDDC
J06
VDDC
J07
VDDC
J22
VDDC
J23
VDDC
M07
VDDC
M22
Pin Assignment—by Signal Name (Continued)
Pin Name
Pin No. Pin Name
Pin No.