參數(shù)資料
型號(hào)： SME1430LGA-480
元件分類(lèi)： 微控制器/微處理器
英文描述： 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587
封裝： CERAMIC, LGA-587
文件頁(yè)數(shù)： 28/60頁(yè)
文件大?。?/td> 646K
代理商： SME1430LGA-480
34
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
L2-cache Write Hits In 2-2-2 Mode
Figure 15 shows the 2-2-2 mode timing for six consecutive write hits to M state lines. Access to the rst tag
(D0_tag) is started by asserting the tag address (A0_tag) in clock cycle 0. The tag data comes back two cycles
later in cycle 2. In clock cycle 3, the UltraSPARC-IIi CPU determines that the access is a hit and that the line is
in Modied (M) state. In the next cycle, a request is made to write the data by asserting the data address
(A0_data). The write data (D0_data) is sent in the next cycle. Separating the address and data by one cycle
reduces the turn-around penalty when reads are immediately followed by writes (Figure 17).
If the line is in M state, then the tag port is available for the tag check of a more recent store during the data
write cycle. In Figure 15 the store buffer is empty when the rst request is made, which is why there is no over-
lap between the tag accesses and the write accesses. In normal operation, if the line is in M state, the tag access
for one write can be done in parallel with the data write step of a previous write phase. In Figure 15, clock
cycles 4 and 5 show overlap of two previous data writes (W0, W1) and tag accesses for two more recent stores
(R4 and R5).
Figure 15. Timing for L2-cache Write Hit to M State Line (2-2-2 mode)
SRAM CYCLE
012345
TSYN_WR_L
R0
R1
R2
TOE_L
R0
R1
R2
ECAT
A0_tag
TDATA
D0_tag
DSYN_WR_L
DOE_L
ECAD
EDATA
CPU CLK
SRAM CLK
6
7
9
R3
R4
R5
R3
R4
R5
W0
A0_data
A1_data
D0_data
D1_data
A1_tag
A2_tag
A3_tag
A4_tag
A5_tag
D1_tag
D2_tag
D3_tag
D4_tag
D5_tag
W1
W2
W3
W4
W0
W1
W2
W3
W4
A2_data
A3_data
A4_data
D2_data
D3_data
overlap
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