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參數(shù)資料
| 型號： | SME1430LGA-480 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封裝： | CERAMIC, LGA-587 |
| 文件頁數(shù)： | 59/60頁 |
| 文件大?。?/td> | 646K |
| 代理商： | SME1430LGA-480 |
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SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
COMPONENT OVERVIEW
In a single-chip implementation, the UltraSPARC-IIi CPU integrates the following components (see Figure 2):
Independently clocked (132 MHz internal, 66 or 33 MHz external) PCI interface, fully decoupled from the
main CPU clock domain and processing operations
PCI bus module (PBM)
PCI I/O memory management unit (IOM) with 16 entries for incoming I/O to physical
mapping/protection
External (L2-cache or E-cache) cache control unit (ECU)
Memory controller unit (MCU), operates both the 144-bit-wide DRAM subsystem and the UPA64S
interface
16-Kilobyte instruction cache (I-cache)
16-Kilobyte data cache (D-cache)
Prefetch, branch prediction and dispatch unit (PDU) containing grouping logic and an instruction buffer
A 64-entry instruction translation lookaside buffer (iTLB) and a 64-entry data translation lookaside buffer
(dTLB)
Integer execution unit (IEU) with two arithmetic logic units (ALUs)
Floating-point unit (FPU) with independent add, multiply and divide/square root sub-units
Graphics unit (GRU) composed of two independent execution pipelines
Load buffer and store buffer unit (LSU), decoupling data accesses from the pipeline
PCI Bus Module (PBM)
The PBM interfaces the UltraSPARC-IIi CPU directly with a 32-bit PCI bus, compatible with the PCI specica-
tion, revision 2.1. The PCI bus can run at speeds of up to 66MHz, typically 33 or 66 MHz. The PBM is
optimized for 16-, 32- and 64-byte transfers, and can support up to four PCI bus masters. The module also
queues pending interrupts received from the Reset/Interrupt/Clock Controller (or RIC, part number
SME2210) chip. The entire PCI address space is noncacheable for CPU references but coherent DMA is sup-
ported (This means that all writes to memory from PCI, and reads from memory, are cache coherent).
Interrupt handling is synchronized to the completion of all prior DMA writes.
IO Memory Management Unit (IOM)
The IOM performs address translations from 32-bit DVMA to 34-bit physical addresses when the
UltraSPARC-IIi CPU is a PCI target (when DVMA read/write access is required). The IOM uses a fully-asso-
ciative 16-entry TLB (translation lookaside buffer). In the case of a TLB miss, the IOM performs a single-level
hardware tablewalk into the large translation storage buffer (TSB) in memory.
External Cache Control Unit (ECU)
The main role of the ECU is to handle I-cache and D-cache misses efciently. The ECU can handle one access
every other cycle to the external cache. Loads that miss in the D-cache cause 16-byte D-cache lls using two
consecutive 8-byte accesses to the L2-cache. Stores are writethrough to the L2-cache and are fully pipelined.
Instruction prefetches that miss the I-cache cause 32-byte I-cache lls using four consecutive 8-byte accesses
to the L2-cache. The L2-cache is parity-protected.
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