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參數(shù)資料
| 型號： | SME1430LGA-480 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封裝： | CERAMIC, LGA-587 |
| 文件頁數(shù)： | 15/60頁 |
| 文件大小： | 646K |
| 代理商： | SME1430LGA-480 |
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SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
SME1430LGA CPU ENHANCEMENTS OVER THE SME1040CGA CPU
Both SME1430LGA and SME1040CGA UltraSPARC-IIi processors are housed in the same LGA package but
the SME1430LGA chip contains functional improvements.
Electrical and Thermal Differences
Core supply voltage Vdd_core is reduced from 2.6 V to 1.9 V.
Power consumption ia reduced at a given frequency with an associated reduction in heat dissipation.
The CPU runs at a reduced junction temperature Tj.
Functional Differences
Synchronizer Stages
Pin P03 has been redened to SYNC_3TO1_MODE.
This function was added to allow for a third synchronizer stage should it prove necessary to ensure stability.
In fact, this feature proved unnecessary and it is recommended that this pin be strapped to ground causing
the processor to operate as the SME1040CGA in this regard.
The UltraSPARC-IIi has a time domain boundary between the CPU core and the PCI primary bus interface.
This pin controls the number of CPU clocks that the CPU waits for the synchronizers to settle. If set to a 1, the
CPU waits for 3 CPU clock cycles. If set to a 0, the CPU waits two CPU clocks. This pin has a weak internal
pull down resistor that is enabled during RAMTEST and RESET modes.
CPU to UPA Clock Frequency Ratio
The CPU to UPA clock ratio is xed by design. In the SME1040CGA the ratio is always 3:1. In SME1430LGA,
the ratio is 4:1.
Memory Controller Bits
A number of timing template bits and their denitions in Mem_Control0 and Mem_Control1 registers have
changed to support higher internal clock rates with the same DIMM timing. For details, refer to the adden-
dum to the UltraSPARC-IIi User’s Manual.
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