參數(shù)資料
型號(hào): Q6701-H6481
廠商: SIEMENS AG
英文描述: Quadruple Transceiver for S/T Interface QUAT-S
中文描述: 四聯(lián)收發(fā)器的S / T接口葛- ?
文件頁(yè)數(shù): 63/72頁(yè)
文件大?。?/td> 1267K
代理商: Q6701-H6481
PEB 2084
Semiconductor Group
63
5.4
Crystal nominal frequency: 7.68 MHz
±
100 ppm
Recommended Oscillator Circuits
Figure 30
Recommended Oscillator Circuits
5.5
T
A
= 0 to 70
°
C;
V
DD
= 5 V
±
5 %
AC testing: Set-up, Hold, Delays
Inputs are driven at
V
DD
– 0.5 V for a logic “1” and 0.45 V for a logic “0”.
Timing measurements are made at 2.0 V for a logic “1” and at 0.8 V for a
logic “0”.
AC Characteristics
Figure 31
Input/Output Wave Form for AC Tests
Jitter
The clock input FSC is used as reference clock to provide the 192 kHz clock for the S/T
interface. In the case of a desynchronous 7.68 MHz clock generated by an oscillator, the
clock FSC should have a jitter of less than 50 ns peak-to-peak.
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