參數(shù)資料
型號(hào): Q6701-H6481
廠商: SIEMENS AG
英文描述: Quadruple Transceiver for S/T Interface QUAT-S
中文描述: 四聯(lián)收發(fā)器的S / T接口葛- ?
文件頁數(shù): 12/72頁
文件大?。?/td> 1267K
代理商: Q6701-H6481
PEB 2084
Semiconductor Group
12
36
CLK1/
IDS
O/I
CLK1:
Clock output 1.536 MHz synchronized to
the trunk line (after reset in high impedance
state, only activated by programming
configuration register)
IOM-Interface Data Rate Select during HW
reset (pin-strapping)
0:
double DCL (normal IOM-2 interface)
1:
single DCL
The value of the input is sampled by the
falling edge of RST. Afterwards the pin may
be used for CLK1 functions.
7.68 MHz clock output
Reset, active high
CEB:
Common echo bit for collision resolution in
logical subscriber LT-S bus configurations
(open drain output, external pull-up resistor
required.)
SSYNC: Superframe synchronization input
D-channel Ready signal to control HDLC hardware in
LT-T mode
(open-drain or push-pull operation identical to pin
IDO)
+ 5 V power supply
IDS:
35
38
17
CLK2
RST
CEB /
SSYNC
O
I
I/O /
I
18
DRDY
O
6, 12,
22, 28,
34, 44
3, 9, 19,
25, 31,
37
V
DD
V
SS
I
I
Reference ground
1.4
Pin No. Symbol
Pin Description
(cont’d)
Input (I)
Output (O)
Function
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