參數(shù)資料
型號(hào): Q6701-H6481
廠商: SIEMENS AG
英文描述: Quadruple Transceiver for S/T Interface QUAT-S
中文描述: 四聯(lián)收發(fā)器的S / T接口葛- ?
文件頁(yè)數(shù): 28/72頁(yè)
文件大?。?/td> 1267K
代理商: Q6701-H6481
PEB 2084
Semiconductor Group
28
Figure 13
Receive Signal Oversampling on S and T Interfaces
The PLL also provides a synchronous 1.536 MHz clock (adaptive timing recovery),
which can be used to synchronize the PCM clocks of the PEB 20550, ELIC, by means of
a XTAL controlled PLL circuit. Refer to
figure 14.
Figure 14
Clock System in LT-S and LT-T Modes
ITD02361
27
30 31
24
21 22
26
29
20
23
11
8
17
14
9
7
12
19
18
13
15 16
Derived 192-kHz Receive Bit Period
1
4
3
5
6
2
33
35
34
32
40
39
38
37
36
28
25
V
SR2
SR1
V
V
TR1
TR2
V
10
-
or
0 V
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