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參數(shù)資料
| 型號(hào)： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁(yè)數(shù)： | 14/72頁(yè) |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
14
2.2
PEB 2084, QUAT-S, provides four independent S/T interfaces, one IOM-2 interface and
one JTAG boundary scan test interface.
Interfaces
2.2.1
S/T Interface
Frame Structure
One frame consists of 48 bits, at a nominal bit rate of 192 kbit/s. Thus each frame carries
two octets of B1, two octets of B2 and 4 bits of D-channel, according to the B1+B2+D
structure defined for the ISDN basic access (the total user data rate is 144 kbit/s). The
beginning of the frame is marked with a F-bit using a code violation (no Mark inversion).
The frame structures for data downstream (from network to subscriber) and for data
upstream (from subscriber to network) are shown in
figure 3
.
Figure 3
Frame Structure at Reference Points S and T (CCITT I.430)
The E-bit (= Echo bit to the D-channel bit) can be controlled via C/I channel and may be
used to carry the “available” / “blocked” information sent by ELIC, PEB 20550. Refer to
chapter 3.3.3
.
ITD02330
DL.
0
1
0
L.
F
B1
E D AF N
B2
E DM
B1
S
D
E
B2
E DL. F L.
48 Bits in 250
μ
s
L.
F
L.
D
L.
B2
L.DL.
B1
L.
D
L.
B2
A
L.
F
L.
D
L.
B1
FL.
L.
D
F = Framing Bit
DC Balancing Bit
=
L
D-Channel Bit
=
D
D-Echo-Channel Bit
=
E
Auxiliary Framing Bit or Q-Bit
=
F
A
Bit set to a Binary Value N
B1 = Bit within B Channel
B2 =
A = Bit used for Activation
S = Subchannel SC1 through SC5 bit position
M = Multiframing Bit
=
N
Bit within B Channel
t
F
A
=
1
2
2 Bits Offset
NT
TE
NT
TE
0
1
0
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