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參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 29/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
29
Since the ELIC generates the IOM-2 clocks (FSC, DCL) for all connected layer-1 and
layer-2 devices, the loop is closed. If several layer-1 devices are operated in LT-T mode,
only one device (one channel in a QUAT-S) may be selected (Configuration Register, bit
RCLK) to deliver the reference clock.
The receive PLL performs tracking every 250
μ
s after detecting a phase difference
between the F/L transition of the receive signal and the recovered clock. A phase
adjustment is done by adding or subtracting 65 ns to or from the 1.536 MHz clock cycle.
Elastic Buffer
The two interfaces (IOM-2 and S/T) of the QUAT-S require a buffer to compensate for
the differences in bit rate between the two interfaces as well as the different round trip
delays of various wiring configurations. The QUAT-S enables intermediate storage of
3
×
B1, 3
×
B2 and 6 D-bits for phase difference and wander absorption.
Moreover, the buffer is designed as a wander-tolerant system, required in LT-T modes
where the QUAT-S is a slave to both interfaces and the data clocks of the two interfaces
have a time dependent phase relationship. The elastic buffer of the QUAT-S
compensates for a maximum phase wander of 50
μ
s peak-to-peak and a slip detector
indicates when this limit is exceeded. Setting the C/W-bit in the Configuration Register
gives a warning when a slip of 25
μ
s is exceeded. An indication (Slip detected) is
released in the C/I channel. However the data may be lost.
The phase relationship between the IOM-2 interface and the S/T interface is arbitrary in
this case.
The transmit frame is shifted (delayed) by two bits with respect to the receive frame.
2.3.4
An incorporated finite state machine controls the activation and deactivation procedures
and communicates with the layer-2 unit via the IOM-2 C/I channel. Each of the four C/I
channels is allocated to its corresponding S/T line interface. Refer to
chapter 3.6.
Activation / Deactivation
2.3.5
The QUAT-S supports two different kinds of frame structures:
a) A Multi-Frame consisting of 20 consecutive S/T frames.
b) A Super-Frame consisting of 2
×
n (n = 1, 2, …) consecutive S/T frames.
S/T Interface Frame Structures Synchronization
Both frames provide an extra layer-1 capacity for information transmission in both
application modes: LT-T and LT-S (refer to
chapter 3.6
, access to S and Q channels).
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相關(guān)代理商/技術(shù)參數(shù) |
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| Q67020-Y149 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y150 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y151 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y152 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:OCTAL BUS TRANSCEIVER |
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