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參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 24/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
24
2.3
Individual Functions
2.3.1
The receiver input stages consist of a differential amplifier, followed by a peak detector
and a set of comparators. Additional noise immunity is achieved by digital oversampling
after the comparators, meaning that the sampling of the received bit is controlled digitally
and dependent on the mode (CONFIGURATION Register).
The peak detector requires at most 2
μ
s to reach the peak value while storing the peak
level for at least 250
μ
s. The data detection thresholds are chosen to 35 % of the peak
voltage to increase the performance in extended passive bus configurations. However
they are never lower than 85 mV. The level detector monitors the line input signals to
detect whether an information is present. In LT-S analog loop-back mode the level
detector monitors its own loop signal and an incoming signal is not recognized.
Transceiver, Analog Connections
Figure 9
Receiver Functional Blocks
The transmitter stage consists of two identical current limited voltage sources, one for
each polarity of output pulses, in order to achieve a ternary pulse shaping. A voltage of
2.1 V is delivered between SXna and SXnb, which yields a current of 7.5 mA over 280
.
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| Q67020-Y149 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
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