參數(shù)資料
型號(hào)： Q6701-H6481
廠商： SIEMENS AG
英文描述： Quadruple Transceiver for S/T Interface QUAT-S
中文描述： 四聯(lián)收發(fā)器的S / T接口葛- ?
文件頁數(shù)： 54/72頁
文件大?。?/td> 1267K
代理商： Q6701-H6481
PEB 2084
Semiconductor Group
54
4
As the QUAT-S contains four PEB 2081, SBCX, cores, it contains four complete register
sets. All registers programming is done via the four IOM monitor channels.
Access to the registers of the QUAT-S are treated as local functions and therefore are
marked with the code “1000” in the first four bits of the message:
Monitor message:
Registers Description
Register Read
An internal register is read by setting the internal address to zero (0
H
) and indicating the
address of the specific register in the bits D(3:0). The bits D(7:4) are set to zero.
E.g. “80
H
01
H
” is the read command for the register 1
H
, the Configuration Register.
The response message from QUAT-S comprises two bytes, the first showing the
address after the local function code, the second showing the register data.
E.g. “81
H
(D7:0)” is the response to a read command on address 1
H
, where D(7:0) is the
content of the Configuration Register.
Register Write
An internal register is written by setting the internal address to the address of the specific
register. The register will then be loaded with the value of D(7:0),
e.g. “81
H
5D
H
” programs the Configuration Register (addr. 1
H
) with the value 5D
H
.
4.1
Read, Address: 0
H
Identification Register
After the read command “80
H
00
H
” according to the procedure described above the
QUAT-S transmits the response “80
H
44
H
”.
The returned value 44
H
of the Identification Register is specific for the PEB 2084,
QUAT
-
S.
Code = 1 0 0 0
Internal address
D7 D6 D5 D4
D3 D2 D1 D0
Code = 1 0 0 0
0 0 0 0
0 0 0 0
register addr. = 01
H
Code = 1 0 0 0
register addr.= 01
H
D7 D6 D5 D4
D3 D2 D1 D0
Code = 1 0 0 0
register addr.
D7 D6 D5 D4
D3 D2 D1 D0
bit 7
0
bit 0
0
Format:
1
0
0
0
1
0
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Q67020-Y153 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:OCTAL BUS TRANSCEIVER
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