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參數(shù)資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯(lián)收發(fā)器的S / T接口葛- ? |
| 文件頁數(shù)： | 48/72頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
48
LT-T Mode, Conditional States
F3 power down
This is the deactivated state of the physical protocol. The receive line awake unit is
active.
F3 power up
This state is similar to “F3 power down”. The state is invoked by a C/I command
TIM = “0000” (or DI static low). After the subsequent activation of the clocks the
“Power Up” message is output.
F3 pending deactivation
The line interface reaches this state after receiving INFO 0 (from states F5 to F8).
From this state an activation is only possible from the line (transition “F3 pend. deact.”
to “F5 unsynchronized”). The power down state may be reached only after receiving
DI.
F4 pending activation
Activation has been requested from the terminal, INFO 1 is transmitted, INFO 0 is still
received, “Power Up” is transmitted in the C/I channel. This state is stable: timer T3
(I.430) is to be implemented in software.
F5/8 unsynchronized
At the reception of any signal from the NT, the QUAT-S ceases to transmit INFO 1,
adapts its receiver circuit, and awaits identification of INFO 2 or INFO 4. This state is
also reached after the line interface has lost synchronism in the states F6 or F7
respectively.
F6 synchronized
When the QUAT-S receives an activation signal (INFO 2), it responds with INFO 3 and
waits for normal frames (INFO 4).
F7 activated
This is the normal active state with the layer-1 protocol activated in both directions.
From state “F6 synchronized”, state F7 is reached almost 0.5 ms after reception of
INFO 4.
F7 slip detected
When a slip is detected between the T interface clocking system and the IOM-2
interface clocks (phase wander greater than 50
μ
s, data may be disturbed, or 25
μ
s if
programmed in the configuration register) the line interface enters this state,
synchronizing again the internal buffer. After 0.5 ms this state is left again.
相關PDF資料 |
PDF描述 |
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| Q67020-Y149 | Octal Latch |
| Q67020-Y150 | Octal Latch |
| Q67020-Y151 | CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y152 | CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67020-Y149 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y150 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Octal Latch |
| Q67020-Y151 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y152 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:CLOCK GENERATOR AND DRIVER FOR SAB8086 FAMILY PROCESSORS |
| Q67020-Y153 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:OCTAL BUS TRANSCEIVER |
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