參數(shù)資料
型號: MSC8256TVT1000B
廠商: Freescale Semiconductor
文件頁數(shù): 58/70頁
文件大?。?/td> 0K
描述: IC DSP 6 CORE 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: StarCore
類型: SC3850 內(nèi)核
接口: 以太網(wǎng),I²C,PCI,RGMII,串行 RapidIO,SGMII,SPI,UART/USART
時(shí)鐘速率: 1.0GHz
非易失內(nèi)存: ROM(96 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 2.50V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Hardware Design Considerations
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
61
3.5
Connectivity Guidelines
Note:
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
1.
GND indicates using a 10 k
Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50 mA through the I/O supply that adds to overall power
consumption.
2.
VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.
Direct connections to the supply may yield DC current up to 50 mA through the I/O supply that adds to overall power
consumption.
3.
Mandatory use of a pull-up or pull-down resistor is clearly indicated as “pull-up/pull-down.” For buses, each pin on
the bus should have its own resistor.
4.
NC indicates “not connected” and means do not connect anything to the pin.
5.
The phrase “in use” indicates a typical pin connection for the required function.
Note:
Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of
subset interface connection.
3.5.1
DDR Memory Related Pins
This section discusses the various scenarios that can be used with either of the MSC8256 DDR ports.
Note:
The signal names in Table 40, Table 41 and Table 42 are generic names for a DDR SDRAM interface. For actual pin
names refer to Table 1.
3.5.1.1
DDR Interface Is Not Used
Table 40. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
Signal Name
Pin Connection
MDQ[0–63]
NC
MDQS[7–0]
NC
MDQS[7–0]
NC
MA[15–0]
NC
MCK[0–2]
NC
MCK[0–2]
NC
MCS[1–0]
NC
MDM[7–0]
NC
MBA[2–0]
NC
MCAS
NC
MCKE[1–0]
NC
MODT[1–0]
NC
MMDIC[1–0]
NC
MRAS
NC
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