參數(shù)資料
型號： MSC8256TVT1000B
廠商： Freescale Semiconductor
文件頁數(shù)： 27/70頁
文件大?。?/td> 0K
描述： IC DSP 6 CORE 1GHZ 783FCPBGA
標準包裝： 1
系列： StarCore
類型： SC3850 內(nèi)核
接口： 以太網(wǎng)，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART
時鐘速率： 1.0GHz
非易失內(nèi)存： ROM（96 kB）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.00V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
33
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled externally.
For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase
(SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use.
2.5.3.2
DC-Level Requirements for PCI Express Configurations
The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The MSC8256
supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The transmitter
specifications are defined in Table 11 and the receiver specifications are defined in Table 12.
Note:
Specifications are valid at the recommended operating conditions listed in Table 3.
Figure 9. Single-Ended Reference Clock Input DC Requirements
Table 11. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential peak-to-peak output voltage
VTX-DIFFp-p
800
1000
1200
mV
1
De-emphasized differential output voltage (ratio)
VTX-DE-RATIO
3.0
3.5
4.0
dB
2
DC differential Tx impedance
ZTX-DIFF-DC
80
100
120
Ω
3
Transmitter DC impedance
ZTX-DC
40
50
60
Ω
4
Notes:
1.
VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
2.
Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a
transition. Measured at the package pins with a test load of 50
Ω to GND on each pin.
3.
Tx DC differential mode low impedance
4.
Required Tx D+ as well as D– DC Impedance during all states
Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input peak-to-peak voltage
VRX-DIFFp-p
120
1000
1200
mV
1
DC differential Input Impedance
ZRX-DIFF-DC
80
100
120
Ω
2
DC input impedance
ZRX-DC
40
50
60
Ω
3
Powered down DC input impedance
ZRX-HIGH-IMP-DC
50
—
ΚΩ
4
Electrical idle detect threshold
VRX-IDLE-DET-DIFFp-p
65
—
175
mV
5
SR[1–2]_REF_CLK
400 mV < SR[1–2]_REF_CLK Input Amplitude < 800 mV
0V
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