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參數資料
| 型號： | MSC8256TVT1000B |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 25/70頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 6 CORE 1GHZ 783FCPBGA |
| 標準包裝： | 1 |
| 系列： | StarCore |
| 類型： | SC3850 內核 |
| 接口： | 以太網，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART |
| 時鐘速率： | 1.0GHz |
| 非易失內存： | ROM（96 kB） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.00V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，FCBGA |
| 供應商設備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
31
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
single-ended mode descriptions below for detailed requirements.
The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V
/ 50 = 8 mA)
while the minimum common mode input level is 0.1 V above GNDSXC. For example, a clock with a 50/50 duty
cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SR[1–2]_REF_CLK and SR[1–2]_REF_CLK inputs cannot drive 50
Ω to GND
SXC DC or
the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled
externally.
The input amplitude requirement is described in detail in the following sections.
2.5.2.3
SerDes Transmitter and Receiver Reference Circuits
Figure 6 shows the reference circuits for SerDes data lane transmitter and receiver.
2.5.3
DC-Level Requirements for SerDes Interfaces
The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, and the SGMII data lines.
2.5.3.1
DC-Level Requirements for SerDes Reference Clocks
The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
Differential Mode
Figure 6. SerDes Transmitter and Receiver Reference Circuits
50
Ω
50
Ω
50
Ω
50
Ω
Transmitter
Receiver
SR[1–2]_TXm
SR[1–2]_RXm
SR[1–2]_TXm
SR[1–2]_RXm
Note: The [1–2] indicates the specific SerDes Interface (1 or 2) and the m indicates the
specific channel within that interface (0,1,2,3). Actual signals are assigned by the
HRCW assignments at reset (see Chapter 5, Reset in the reference manual for details)
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| MSC8256TVT800B | 功能描述:數字信號處理器和控制器 - DSP, DSC DSPStarcore 6-core RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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