參數(shù)資料
型號(hào)： MSC8256TVT1000B
廠商： Freescale Semiconductor
文件頁數(shù)： 26/70頁
文件大?。?/td> 0K
描述： IC DSP 6 CORE 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝： 1
系列： StarCore
類型： SC3850 內(nèi)核
接口： 以太網(wǎng)，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART
時(shí)鐘速率： 1.0GHz
非易失內(nèi)存： ROM（96 kB）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.00V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
32
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, the maximum average current requirements sets the requirement for
average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 7 shows the SerDes reference
clock input requirement for DC-coupled connection scheme.
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to
swing below and above the command mode voltage GNDSXC. Figure 8 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
Single-Ended Mode
— The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing)
must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SR[1–2]_REF_CLK either left
unconnected or tied to ground.
— The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV. Figure 9 shows the SerDes
reference clock input requirement for single-ended signalling mode.
Figure 7. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled)
SR[1–2]_REF_CLK
Vmax < 800 mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
SR[1–2]_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
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