參數(shù)資料
型號(hào): MSC8256TVT1000B
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 46/70頁(yè)
文件大小: 0K
描述: IC DSP 6 CORE 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: StarCore
類型: SC3850 內(nèi)核
接口: 以太網(wǎng),I²C,PCI,RGMII,串行 RapidIO,SGMII,SPI,UART/USART
時(shí)鐘速率: 1.0GHz
非易失內(nèi)存: ROM(96 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 2.50V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
50
Figure 23 shows the AC test load for the timers.
2.6.5
Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8256 Reference
Manual.
2.6.5.1
Management Interface Timing
Table 33 lists the timer input Ethernet controller management interface timing specifications shown in Figure 24.
Figure 23. Timer AC Test Load
Table 33. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
GE_MDC frequency
fMDC
—2.5
MHz
GE_MDC period
tMDC
400
ns
GE_MDC clock pulse width high
tMDC_H
160
ns
GE_MDC clock pulse width low
tMDC_L
160
ns
GE_MDC to GE_MDIO delay2
tMDKHDX
10
70
ns
GE_MDIO to GE_MDC rising edge setup time
tMDDVKH
20
ns
GE_MDC rising edge to GE_MDIO hold time
tMDDXKH
0—
ns
Notes:
1.
Program the GE_MDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz to
achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8256 Reference Manual for
configuration details.
2.
The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
Output
Z0 = 50 Ω
VDDIO/2
RL = 50 Ω
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