參數(shù)資料
型號： MSC8256TVT1000B
廠商： Freescale Semiconductor
文件頁數(shù)： 20/70頁
文件大?。?/td> 0K
描述： IC DSP 6 CORE 1GHZ 783FCPBGA
標準包裝： 1
系列： StarCore
類型： SC3850 內(nèi)核
接口： 以太網(wǎng)，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART
時鐘速率： 1.0GHz
非易失內(nèi)存： ROM（96 kB）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.00V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
27
2.5.1.1
DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 6 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM.
Note:
At recommended operating conditions (see Table 3) with VDDDDR =1.8 V.
2.5.1.2
DDR3 (1.5V) SDRAM DC Electrical Characteristics
Table 7 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM.
Note:
At recommended operating conditions (see Table 3) with VDDDDR =1.5 V.
Table 6. DDR2 SDRAM Interface DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O reference voltage
MVREF
0.49
× V
DDDDR
0.51
× V
DDDDR
V
2, 3, 4
Input high voltage
VIH
MVREF + 0.125
VDDDDR +0.3
V
5
Input low voltage
VIL
–0.3
MVREF – 0.125
V
5
I/O leakage current
IOZ
–50
50
μA6
Output high current (VOUT (VOH) = 1.37 V)
IOH
–13.4
—
mA
7
Output low current (VOUT (VOL) = 0.33 V)
IOL
13.4
—
mA
7
Notes:
1.
VDDDDR is expected to be within 50 mV of the DRAM VDD supply voltage at all times. The DRAM and memory controller can
use the same or different sources.
2.
MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3.
VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal
to MVREF with a minimum value of MVREF – 0.4 and a maximum value of MVREF + 0.04 V. VTT should track variations in the
DC-level of MVREF.
4.
The voltage regulator for MVREF must be able to supply up to 300 μA.
5.
Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.
6.
Output leakage is measured with all outputs are disabled, 0 V
≤ V
OUT ≤ VDDDDR.
7.
Refer to the IBIS model for the complete output IV curve characteristics.
Table 7. DDR3 SDRAM Interface DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O reference voltage
MVREF
0.49
× V
DDDDR
0.51
× V
DDDDR
V
2,3,4
Input high voltage
VIH
MVREF + 0.100
VDDDDR
V5
Input low voltage
VIL
GND
MVREF – 0.100
V
5
I/O leakage current
IOZ
–50
50
μA6
Notes:
1.
VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. The DRAM and memory controller can use the same or
different sources.
2.
MVREF is expected to be equal to 0.5 × VDDDDR and to track VDDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±1% of the DC value.
3.
VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF with a minimum value of MVREF – 0.4 and a maximum value of MVREF + 0.04 V. VTT should track variations
in the DC-level of MVREF.
4.
The voltage regulator for MVREF must be able to supply up to 250 μA.
5.
Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.
6.
Output leakage is measured with all outputs are disabled, 0 V
≤ V
OUT ≤ VDDDDR.
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