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| 型號： | MSC8256TVT1000B |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 28/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 6 CORE 1GHZ 783FCPBGA |
| 標準包裝： | 1 |
| 系列： | StarCore |
| 類型： | SC3850 內核 |
| 接口： | 以太網，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART |
| 時鐘速率： | 1.0GHz |
| 非易失內存： | ROM（96 kB） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.00V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
34
2.5.3.3
DC-Level Requirements for Serial RapidIO Configurations
This sections provided various DC-level requirements for Serial RapidIO Configurations.
Note:
Specifications are valid at the recommended operating conditions listed in Table 3.
2.5.3.4
DC-Level Requirements for SGMII Configurations
Note:
Specifications are valid at the recommended operating conditions listed in Table 3
Table 15 describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are
measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) as shown in Figure 10.
Notes:
1.
VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
2.
Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to
detect (the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all
unconfigured lanes of a port.
3.
Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50
Ω to
GND on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state
of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of
a port.
4.
Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode
impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect
circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx
ground.
5.
VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ –VRX-D–|. Measured at the package pins of the receiver
Table 13. Serial RapidIO Transmitter DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Output voltage
VO
–0.40
—
2.30
V
1
Long run differential output voltage
VDIFFPP
800
—
1600
mVp-p
—
Short run differential output voltage
VDIFFPP
500
—
1000
mVp-p
—
Note:
Voltage relative to COMMON of either signal comprising a differential pair.
Table 14. Serial RapidIO Receiver DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
VIN
200
—
1600
mVp-p
1
Notes:
1.
Measured at receiver.
Table 15. SGMII DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Output high voltage
VOH
——
XVDD_SRDS-Typ/2 + |VOD|-max/2
mV
1
Output low voltage
VOL
XVDD_SRDS-Typ/2 – |VOD|-max/2
—
mV
1
Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
Notes
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