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參數(shù)資料
| 型號(hào)： | MSC8256TVT1000B |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 24/70頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DSP 6 CORE 1GHZ 783FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | StarCore |
| 類(lèi)型： | SC3850 內(nèi)核 |
| 接口： | 以太網(wǎng)，I²C，PCI，RGMII，串行 RapidIO，SGMII，SPI，UART/USART |
| 時(shí)鐘速率： | 1.0GHz |
| 非易失內(nèi)存： | ROM（96 kB） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.00V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤(pán) |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
30
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (VOD) has
the same amplitude as each signal single-ended swing. The differential output signal ranges between 500 mV and –500 mV. In
other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV.
The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.5.2.2
SerDes Reference Clock Receiver Characteristics
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SR1_REF_CLK/SR1_REF_CLK or SR2_REF_CLK/SR2_REF_CLK.
Figure 5 shows a receiver reference diagram of the SerDes reference clocks.
The characteristics of the clock signals are as follows:
The SerDes reference clock receiver reference circuit structure is as follows:
—The SR[1–2]_REF_CLK and SR[1–2]_REF_CLK are internally AC-coupled differential inputs as shown in
Figure 5. Each differential clock input (SR[1–2]_REF_CLK or SR[1–2]_REF_CLK) has on-chip 50-
Ω
termination to GNDSXC followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SR[1–2]_TX, for example)
from the non-inverting signal (SR[1–2]_TX, for example) within a differential pair. There is only one
signal trace curve in a differential waveform. The voltage represented in the differential waveform is
not referenced to ground. Refer to Figure 16 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each conductor of a
balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out =(VSR[1–2]_TX +VSR[1–2]_TX) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
complimentary output voltages within a differential pair. In a system, the common mode voltage may
often differ from one component’s output to the other’s input. It may be different between the receiver
input and driver output circuits within the same component. It is also referred to as the DC offset on
some occasions.
Figure 5. Receiver of SerDes Reference Clocks
Table 10. Differential Signal Definitions (continued)
Term
Definition
Input
Amp
50
Ω
50
Ω
SR[1–2]_REF_CLK
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