參數(shù)資料
型號(hào): MSC8256TVT1000B
廠商: Freescale Semiconductor
文件頁數(shù): 47/70頁
文件大?。?/td> 0K
描述: IC DSP 6 CORE 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: StarCore
類型: SC3850 內(nèi)核
接口: 以太網(wǎng),I²C,PCI,RGMII,串行 RapidIO,SGMII,SPI,UART/USART
時(shí)鐘速率: 1.0GHz
非易失內(nèi)存: ROM(96 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 2.50V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
51
2.6.5.2
RGMII AC Timing Specifications
Table 34 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 35 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Figure 24. MII Management Interface Timing
Table 34. RGMII at 1 Gbps2 with On-Board Delay3 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)4
tSKEWT
–-0.5
0.5
ns
Data to clock input skew (at receiver) 4
tSKEWR
1—
2.6
ns
Notes:
1.
At recommended operating conditions with VDDIO of 2.5 V ± 5%.
2.
RGMII at 100 Mbps support is guaranteed by design.
3.
Program GCR4 as 0x00000000.
4.
This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and
less than 2.0 ns is added to the associated clock signal.
Table 35. RGMII at 1 Gbps2 with No On-Board Delay3 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)4
tSKEWT
–2.6
–1.0
ns
Data to clock input skew (at receiver)4
tSKEWR
–0.5
0.5
ns
Notes:
1.
At recommended operating conditions with VDDIO of 2.5 V ± 5%.
2.
RGMII at 100 Mbps support is guaranteed by design.
3.
GCR4 should be programmed as 0x000CC330.
4.
This implies that PC board design requires clocks to be routed with no additional trace delay
GE_MDC
GE_MDIO
(Input)
(Output)
tMDC
tMDDXKH
tMDDVKH
tMDKHDX
tMDC_H
tMDC_L
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