參數(shù)資料
型號： MK50H28Q25/XX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 4/64頁
文件大?。?/td> 429K
代理商： MK50H28Q25/XX
INIT BLOCK
PTR TO INIT
MODE
PTR TO ALT
PTR TO STATUS
PTR TO CT
ADDRESS
LOOKUP
TABLE
RING0
XMIT
BUFF
0
BUFF ADDRESS
BUFF SIZE
BUFF MSG CNT
DESC 0
TIMER VALUES
ACT. CHNL
(1 ENTRY/ACT. CHNL)
BUFFERS
DATA
ACTIVE CHNL. 1
ACTIVE CHNL. N
TABLE
CONTEXT
RING N
XMIT
BUFF SIZE
BUFF MSG CNT
DESC 0
DESC 1
DESC M
BUFF
M
DESC 1
DESC N
BUFF ADDRESS
BUFF
1
BUFF
1
BUFF
N
LMI ERROR
STATUS
BUFFER
CSR2, CSR3
COUNTERS
BUFF
0
RX RING N
DESC 0
DESC 1
BUFF
0
BUFF
Y
DESC Y
BUFFERS
DATA
BUFF ADDRESS
BUFF SIZE
BUFF MSG CNT
BUFF
1
RX RING 0
DESC 0
DESC 1
BUFF
0
BUFF
X
DESC X
BUFFERS
DATA
BUFF ADDRESS
BUFF SIZE
BUFF MSG CNT
BUFF
1
DESC RING PTRS
ACTIVE CHNL. 0
CONG STA TISTICS
DLCI / ADDRESS
CONG STATISTIC S
DLCI / ADDRESS
DESC RING PTRS
CONG STA TISTICS
DLCI / ADDRESS
DESC RING PTRS
BUFFER
(DLCI 0
to
DLCI 1024
PRIORITY DLCI
BLOCK
or
DLCI 8192)
RX INTERRUPT RING
DESC 0
DESC 1
DESC 127
RX CT Address
Current RX Desc
Service Bit
TX INTERRUP T RING
DESC 0
DESC 1
DESC 127
TX CT Address
Current TX Desc
Service Bit
PTR TO TINT DR
PTR TO RINT DR
Figure 3: MK50H28 Memory Management Structure
MK50H28
12/64
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MK50N512CLQ100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
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