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參數(shù)資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 16/64頁 |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
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BIT
NAME
DESCRIPTION
15
CYCLE
Setting this bit selects a shorter DMA Cycle (5 vs 6 SYSCLK)
14
EIBEN
Extended Initialization Block Enable. Setting this bit causes the MK50H28
to use an
extended Initialization Block which uses all of IADR+08 as a 16-bit scaler and moves nN1
to the upper byte of IADR+40.
13
DLCI1K
Setting this bit causes the chip to recognize the 8192 possible DLCIs.If this bit is cleared,
the chip will ignore all received frames with DLCI greater than 1023.
12
LMICH
CHLMI Channel Select: Setting this bit to 0 causes frames received on DLCI 0 to be
treated as LMI frames.. Setting it to 1 causes frames received on DLCI 1023 to be treated
as LMI frames. NOTE: Regardless of the setting of this bit, only the first entry in the
Context Table table (CT0) will be used for transmission and reception of LMI
frames.
11
TRAN
Should be set only if frames need to be transmitted without protocol processing from the
transmit buffers. With this bit set, the chip will not prepend an address field when
transmitting data from the buffers, but rather, the buffers should have both address and
data information for proper Frame Relay protocol.
10
0
Reserved. Must be written as zeroes.
09
ANXD
Setting this bit enables operation in conformance with T1.617 Annex D specifications.
With ANXD=0, the MK50H28 operates in conformance with CCITTQ.933 Annex A.
08
TDMD
Transmit Demand. Setting this bit causes the MK50H28 to ignore the TP (Transmit Poll
timer) and continuously poll all Context Table entries until TDMD is cleared by the host.
07:00
IADR
The high order 8 bits of the address of the first word in the Initialization Block. IADR must
be written by the Host prior to issuing an Init Request primitive.
4.1.2.3 Control and Status Register 2 (CSR2)
RAP<3:1> = 2
1
5
1
0
1
4
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
IADR<23:16>
T
R
A
N
A
L
M
I
C
H
D
L
C
I
1
K
0
T
D
M
D
C
Y
C
L
E
I
B
E
N
X
D
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1>
=3
1
5
1
0
1
4
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
0
IADR <15:00>
BIT
NAME
DESCRIPTION
15:00
IADR
The low order 16 bits of the address of the first word in the Initialization Block. Must be
written by the Host prior to issuing an Init Request primitive. The Initialization block must
begin on a word boundary.
MK50H28
23/64
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