參數(shù)資料
型號(hào)： MK50H28Q25/XX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 25/64頁(yè)
文件大?。?/td> 429K
代理商： MK50H28Q25/XX
4.2.3 Context Table (CT) Address
1
5
1
4
1
3
0
7
0
8
1
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
IADR + 16
IADR + 18
CTADR <15:00>
0
CTADR <23:16>
00000
000
BIT
NAME
DESCRIPTION
15:08
0
Reserved, must be written as a zero.
07:00/15:00
CTADR
CONTEXT TABLE ADDRESS. The CT Address must begin on a word boundary.
4.2.4 Context Table (CT)
The MK50H28 performs multi-tasking by means of a Context Table (CT). Each entry in this table con-
tains all the information relevant to one individual DLCI channel. Associated with each CTentry are a set
of descriptor rings that are used for transmitting and receiving frames. Through the use of the SRIP field
in the CT, more than on CT entry (or DLCI) may share the same Receive Rescriptor Ring while still
keeping the individual DLCI statistics and error counters separately in each CT entry. All channel en-
tries, except the LMI Channel (CT0), have equal priority. Each channel entry requires 16 words (or 32
bytes) of memory in the CT, and all channel entries in the Context Table are identical.
The MK50H28 sequentially scans each entry in the CT for any available frames to be transmitted, unless
the ENIDX bit is set or scanning is interrupted by setting PTDMD in CSR2. If the MK50H28 finds the
ENIDX bit set when scanning a CT entry, it unconditionally jumps to the CT entry pointed to by the
IDXPTR field. Finally, the end of CT is marked by setting the EOCT bit in the last channel entry. In the
Information Transfer phase, the MK50H28 is initialized to start transmission from the first non-LMI CT
entry (the second CT entry: CT1). Upon finding the TXRDY bit set, it then reads the Transmit Descriptor
Ring entry determined by the Transmit DescriptorRing Address and the CURXD index found in the CT. If
the MK50H28 then finds the OWNA bit set in the Transmit Message Descriptor 0, it will transmit a frame
with a DLCI found in the CT entry (at CTADR+06 & +08) and with data from the buffer pointed to by the
Transmit Descriptor Ring entry. The MK50H28 automatically calculates and appends the correct CRC.
The MK50H28 reception process uses an Address Lookup Table (ALT) mechanism further specified in
4.2.6. The ALT contains a 1 word entry for each DLCI (selectable between 1024 or 8192 DLCIs) which
consits of an index to the Context Table and an ACTIVE bit to indicate whether frames received with the
associated DLCI should be processed or ignored. When a frame is received, its DLCI is used as an off-
set from the beginning of the ALT (containing the index to the CT for DLCI 0). If the ACTIVE bit is set for
the ALT entry corresponding to the DLCI of the received frame, then the MK50H28 will proceed to ac-
cess the CT entry pointed to by that ALT entry. The CT entry contains the address of the start of the
corresponding Received Descriptor Ring and an index to the current descriptor in that ring. Each entry in
the descriptor ring in turn points to a buffer into which the received frame is written. A received frame
may span more than one buffer by use of the ELF buffer chaining mechanism described in 4.3.
Therefore, the MK50H28 transmission process is similar to the reception process except that it does not
use the ALT (nor the ACTVE bit therein), but rather the TXRDY bit in the CT entry is used to determine
what channels are active for transmission. In addition, both the ACTVE bit in the ALT and the RXRDY bit
in CT must be set in order to receive frames.
MK50H28
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