參數(shù)資料
型號： MK50H28Q25/XX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 20/64頁
文件大小： 429K
代理商： MK50H28Q25/XX
4.2 Initialization / Priority DLCI Block
MK50H28 initialization includes the reading of the Initialization Block in the off-chip memory to obtain the
operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, the first
16 words of the Initialization block are read by the MK50H28. The remainder of the Initialization block
will be read as needed by the MK50H28. Memory at IADR+32 - IADR+38 should always be initialized
with 0’s prior to issuing the Init Primitive. Any changes to IADR+00 - IADR+31 after initialization require
that the device be stopped and Init primitive be issued again in order to take effect. It is not necessary
that the device be re-initialized after changes to bits in the CSRs (Control and Status Registers).
MODE
BASE ADDRESS
HIGHER ADDR
IADR+00
IADR+02
IADR+04
IADR+06
IADR+08
IADR+10
IADR+12
IADR+14
RESERVED
Counter dN1 (Max Frame Length)
IADR+16
IADR+18
IADR+20
IADR+22
SCALER
Timer nT1 / T391
Timer nT2 / T392
Timer TP
CTADR <15:00>
ALTADR <23:16>
ALTADR <15:00>
IADR+24
IADR+28
Counter nN1/N391
CTADR <23:16>
RESERVED
TINTADR<23:16>
RINTADR <23:16>
RESERVED
SBA <15:00>
IADR+40
IADR+44
ERROR COUNTERS
PRIORITY DLCI
IADR+96
THRU
IADR+XX
BLOCK
THRU
IADR+89
Counter nN1
SBA <15:00>
(If EIBEN=1)
IADR+42
TINTADR <23:16>
RINTADR<23:16>
RESERVED
Ntwk N393
Ntwk N392
User N393
/ nN3
User N392
/ nN2
and STATISTICS
RESERVED
(256 Entries Maximum)
RESERVED-Must be written with 0’s
IADR+32-38
Figure 8: Initialization / Priority DLCI Block
MK50H28
27/64
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