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參數(shù)資料
| 型號(hào)： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 3/64頁(yè) |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
a fixed size of 128 entries each. Each entry will
consist of two 16-bit words containing the24-bit
address of the context table entry (XCTADR or
RCTADR) corresponding to the interrupt, a 7-bit
field for the descriptor index (CURXD or CURRD)
into the associated descriptor ring,
and a bit
SRVC which is used to indicate whether the inter-
rupt has been serviced. The SRVC bit is set by
the MK50H28 when it writes an interrupt to the in-
terrupt ring, and it should be cleared by the host
when it services the interrupt. If the MK50H28 at-
tempts to write an interrupt to the interrupt de-
scriptor ring and finds that SRVC is not clear then
it will issue a Provider Primitive 7 to indicate an
Interrupt Ring MISS (with PPARM=0 to indicate a
Receive Interrupt Ring MISS or PPARM=1 to indi-
cate a Transmit Interrupt Ring MISS).
3.2.2 Address Lookup Table(ALT)
The ALT contains the maximum of 1024 or 8192
addresses formed by the Data Link Connection
Identifier (DLCI). The MK50H28 can support upto
4 octets of address field. The ALT is used to iden-
tify which of the 1024 or 8192 addresses are ac-
tive. For each active channel it has an Index to
the Context Table(CT). The ALT is only used by
the receive process of the MK50H28.
3.2.3 Context Table(CT)
The MK50H28 performs multi-tasking by means
of a Context Table. Each entry in this table con-
tains all the information relevant to one DLCI
channel. Associated with each DLCI are a set of
descriptor rings that are used for transmitting and
receiving frames. All channel entries, except the
LMI Channel,, have equal priority. The MK50H28
scans each entry in the CT sequentially, or
through the use of an index pointer mechanism,
for any available frames to be transmitted. When
a User Primitive 8 with UPARM=2 is issued to the
MK50H28. polling of the LMI/LIV channel will be
enabled to occur between each poll of the other
CT entries.
3.2.4 Transmit Descriptor Ring(s)
The transmit descriptor ring is a circular queue of
tasks that point to data buffers. A variable number
of buffers may be queued-up on a descriptor ring
awaiting execution by the MK50H28.
The de-
scriptor ring has a segment assigned to each
buffer.
Each segment holds a pointer for the
starting address of the buffer, and holds values
for the length of the buffer and the length of the
frame to be transmitted. Each segment also con-
tains an OWNA control bit to denote whether the
MK50H28, or the HOST ”owns” the buffer. For
transmit, when the MK50H28 owns the buffer, the
MK50H28 is allowed and commanded to transmit
the contents of the buffer. When the MK50H28
does not own the buffer, it will not transmit the
data in that buffer.
3.2.5 Receive Descriptor Ring(s)
The receive descriptor ring is circular queue of
tasks that point to data buffers. A variable number
of buffers may be queued-up on a descriptor ring
awaiting execution by the MK50H28.
The de-
scriptor ring has a segment assigned to each
buffer.
Each segment holds a pointer for the
starting address of the buffer, and holds values
for the length of the buffer and the length of the
frame received. Each segment also contains an
OWNA
control
bit
to
denote
whether
the
MK50H28, or the HOST ”owns” the buffer. For
receive, when the MK50H28 owns the buffer, the
MK50H28 may place received data into that buff-
er.
Conversely, when the MK50H28 does not
own a receive buffer, it will not place received
data in that buffer.
3.2.6 Frame Format
The frame format supported by the MK50H28 is
shown below. Each frame may consist of a pro-
grammable number of leading flag patterns
(01111110), an address field, an information field,
an FCS (CRC) of either 16 or 32 bits, and a trail-
ing flag pattern.
The number of leading flags
transmitted is programmable through the Mode
Register in the Initialization Block. The MK50H28
is capable of transmitting and receiving a single
flag between adjacent frames.
TRANSMITTED FIRST
3.2.7 MK50H28 Supported Frame Types
The MK50H28 supports all frame types shown in
Table 1. In LMI, both User and Network Modes
of operation, along with ”O(jiān)ptional Bidirectional
Network Procedures” (Annex D, ANSI T1.617 -
1991) are supported.
ADDRESS
INFO
FLAG
16/24/32
8*n
8
FLAG
FCS
8
16/32
MK50H28
11/64
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