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參數(shù)資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 22/64頁 |
| 文件大小： | 429K |
| 代理商： | MK50H28Q25/XX |
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BIT
NAME
DESCRIPTION
02:00
LBACK
Loopback Control puts MK50H28 into one of several loopback configurations.
LBACK
DESCRIPTION
0
Normal operation. No loopback.
4
Simple loopback. Receive data and clock are driven internally by
transmit data and clock. Transmit clock must be supplied externally
5
Clockless loopback. Receive data is driven internally by transmit data.
Transmit and receive clocks are driven by SYSCLK divided by 8.
6
Silent loopback. Same as simple loopback with td pin forced to all ones.
7
Silent clockless loopback. Combination of Silent and Clockless
loopbacks. Receive data is driven internally by transmit data, transmit
and receive clocks are driven by SYSCLK divided by 8. The TD pin is
forced to all ones.
4.2.2 Timers/Counters
There are 8 independent counter-timers. The lower 8 bits of IADR+08 are used as a scaler for nT1,
nT2 and TP. The scaler is driven by a clock which is 1/32 of SYSCLK. The dN1 is a 16 bit counter and
is used to count the number of bytes in a frame. The counters nN1, nN2, and nN3 are used for the LMI
frames. The Host will write the periods of all the timers/counters into the Initialization Block.
IADR + 08
SCALER
IADR + 10
TIMER nT1 / T391
IADR + 12
IADR + 14
TIMER TP
IADR + 06
COUNTER dN1
1
5
1
4
1
3
0
7
0
8
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
IADR + 04
User N393/nN3
COUNTER nN1 / N391
TIMER nT2 / T392
User N392/nN2
Ntwk N393
Ntwk N392
MK50H28
29/64
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