參數(shù)資料
型號： MB9AF312MPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80
封裝： 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 99/114頁
文件大?。?/td> 1357K
代理商： MB9AF312MPMC
85
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
15.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks
involved when changing TCNT0 when using the output compare Unit, independently of whether the Timer/Counter is
running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in
incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is
downcounting.
The setup of the OC0x should be performed before setting the data Direction register for the port pin to output. The easiest
way of setting the OC0x value is to use the force output compare (FOC0x) strobe bits in normal mode. The OC0x registers
keep their values even when changing between waveform generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will
take effect immediately.
15.6
Compare Match Output Unit
The compare output mode (COM0x1:0) bits have two functions. The waveform generator uses the COM0x1:0 bits for
defining the output compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control the OC0x pin output
source. Figure 15-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O registers,
I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT)
that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x
register, not the OC0x pin. If a system reset occur, the OC0x register is reset to “0”.
Figure 15-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the output compare (OC0x) from the waveform generator if either of the
COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the data direction register
(DDR) for the port pin. The data direction register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x
value is visible on the pin. The port override function is independent of the waveform generation mode.
The design of the output compare pin logic allows initialization of the OC0x state before the output is enabled. Note that
some COM0x1:0 bit settings are reserved for certain modes of operation (see Section 15.9 “Register Description” on page
DA
T
A
BUS
0
1
Q
D
COMnx1
COMnx0
FOCn
OCnx
Waveform
Generator
Q
D
PORT
Q
D
DDR
OCnx
Pin
clkI/O
相關(guān)PDF資料
PDF描述
MB9AF312LPMC 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64
MB9AF311NPMC 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
MB9AF316NPMC RISC MICROCONTROLLER, PQFP100
MB9AF314NPMC RISC MICROCONTROLLER, PQFP100
MB9AF312NPF RISC MICROCONTROLLER, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB9AF314LAPMC1-G-JNE2 制造商:FUJITSU 功能描述:
MB9AF314LAPMC-G-JNE2 制造商:Fujitsu 功能描述:Bulk
MB9AF314LAQN-G-AVE2 功能描述:ARM? Cortex?-M3 FM3 MB9A310A Microcontroller IC 32-Bit 40MHz 256KB (256K x 8) FLASH 64-QFN Exposed Pad (9x9) 制造商:cypress semiconductor corp 系列:FM3 MB9A310A 包裝:托盤 零件狀態(tài):有效 核心處理器:ARM? Cortex?-M3 核心尺寸:32-位 速度:40MHz 連接性:CSIO，I2C，LIN，UART/USART，USB 外設(shè):DMA，LVD，POR，PWM，WDT I/O 數(shù):51 程序存儲容量:256KB（256K x 8） 程序存儲器類型:閃存 EEPROM 容量:- RAM 容量:32K x 8 電壓 - 電源（Vcc/Vdd）:2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 9x12b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 105°C（TA） 封裝/外殼:64-VFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN 裸露焊盤（9x9） 標準包裝:260
MB9AF314LPMC1-ESE1 制造商:FUJITSU 功能描述:
MB9AF314LPMC1-GE1 制造商:FUJITSU 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*