參數(shù)資料
型號(hào)： MB9AF312MPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80
封裝： 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 103/114頁
文件大?。?/td> 1357K
代理商： MB9AF312MPMC
89
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Figure 15-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to
generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the
COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is
set. This option is not available for the OC0B pin (see Table 15-7 on page 93). The actual OC0x value will only be visible on
the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the
OC0x register at the compare match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the
OC0x register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the phase
correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the
output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
At the very start of period 2 in Figure 15-7 OCnx has a transition from high to low even though there is no compare match.
The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without
compare match.
●
OCRnx changes its value from MAX, like in Figure 15-7. When the OCR0A value is MAX the OCn pin value is the
same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCnx value at
MAX must correspond to the result of an up-counting compare match.
●
The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the compare match
and hence the OCnx change that would have happened on the way up.
123
TCNTn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCnx
Period
TOVn Interrupt
Flag Set
OCRnx Update
OCnx Interrupt
Flag Set
fOCnxPCPWM
fclk_I/O
N 510
×
-------------------
=
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