參數(shù)資料
型號： MB9AF312MPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80
封裝： 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 107/114頁
文件大小： 1357K
代理商： MB9AF312MPMC
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
92
Table 15-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Table 15-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.
Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the output compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting.Table 15-5
shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).
Table 15-3. Compare Output Mode, Fast PWM Mode(1)
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
0
1
WGM02 = 0: Normal port operation, OC0A disconnected.
WGM02 = 1: Toggle OC0A on compare match.
1
0
Clear OC0A on compare match, set OC0A at BOTTOM,
(non-inverting mode).
1
Set OC0A on compare match, clear OC0A at BOTTOM,
(inverting mode).
Note:
1.
A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is
ignored, but the set or clear is done at BOTTOM. See Section 15.7.3 “Fast PWM Mode” on page 87 for more
details.
Table 15-4. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
0
1
WGM02 = 0: Normal port operation, OC0A disconnected.
WGM02 = 1: Toggle OC0A on compare match.
1
0
Clear OC0A on compare match when up-counting. Set OC0A on compare match
when down-counting.
1
Set OC0A on compare match when up-counting. Clear OC0A on compare match
when down-counting.
Note:
1.
A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 16.9.4 “Phase Correct PWM Mode” on page 111 for
more details.
Table 15-5. Compare Output Mode, non-PWM Mode
COM0B1
COM0B0
Description
0
Normal port operation, OC0B disconnected.
0
1
Toggle OC0B on compare match
1
0
Clear OC0B on compare match
1
Set OC0B on compare match
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