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| 型號(hào)： | MB9AF312MPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁(yè)數(shù)： | 47/114頁(yè) |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF312MPMC |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
38
10.10.3 Brown-out Detector
If the brown-out detector is not needed by the application, this module should be turned off. If the brown-out detector is
enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption. Refer to
Section 11.5 “Brown-out Detection” on page 43 for details on how to configure the brown-out detector.
10.10.4 Internal Voltage Reference
The internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the ADC.
If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will
not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If
the reference is kept on in sleep mode, the output can be used immediately. Refer to
Section 11.7 “Internal Voltage Reference” on page 44 for details on the start-up time.
10.10.5 Watchdog Timer
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it
will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute
significantly to the total current consumption. Refer to Section 11.8 “Watchdog Timer” on page 45 for details on how to
configure the watchdog timer.
10.10.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure
that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped,
the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section
Section 14.2.5 “Digital Input Enable and Sleep Modes” on page 68 for details on which pins are enabled. If the input buffer is
enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input
pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the digital input
disable registers (DIDR1 and DIDR0). Refer to Section 23.3.3 “DIDR1 – Digital Input Disable Register 1” on page 212 and
10.10.7 On-chip Debug System
If the on-chip debug system is enabled by the DWEN fuse and the chip enters sleep mode, the main clock source is enabled
and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current
consumption.
10.11 Register Description
10.11.1 SMCR – Sleep Mode Control Register
The sleep mode control register contains control bits for power management.
Bits [7:4]: Reserved
These bits are unused in the Atmel ATmega48PA/88PA/168PA, and will always be read as zero.
Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 10-2.
Bit
7654
3210
––––
SM2
SM1
SM0
SE
SMCR
Read/Write
RRRR
R/W
Initial Value
0000
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