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參數(shù)資料
| 型號： | MB9AF312MPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 100/114頁 |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF312MPMC |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
86
15.6.1 Compare Output Mode and Waveform Generation
The waveform generator uses the COM0x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the
COM0x1:0 = 0 tells the waveform generator that no action on the OC0x register is to be performed on the next compare
match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 91. For fast PWM mode, refer to
Table 15-3 on page 92, and for phase correct PWM refer to Table 15-4 on page 92.
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.
15.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of
the waveform generation mode (WGM02:0) and compare output mode (COM0x1:0) bits. The compare output mode bits do
not affect the counting sequence, while the waveform generation mode bits do. The COM0x1:0 bits control whether the
PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits
control whether the output should be set, cleared, or toggled at a compare match
For detailed timing information refer to Section 15.8 “Timer/Counter Timing Diagrams” on page 90.
15.7.1 Normal Mode
The simplest mode of operation is the normal mode (WGM02:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value
(TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV0) will be
set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth bit, except
that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag,
the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter
value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate
waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
15.7.2 Clear Timer on Compare Match (CTC) Mode
In clear timer on compare or CTC mode (WGM02:0 = 2), the OCR0A register is used to manipulate the counter resolution. In
CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top
value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 15-5. The counter value (TCNT0) increases until a compare match
occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.
Figure 15-5. CTC Mode, Timing Diagram
12
TCNTn
(COMnA1:0 = 1)
OCn
(Toggle)
Period
3
OCnx Interrupt Flag Set
4
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