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1
1-21
OVERVIEW
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
1.4 Pin Assignments
Note 1: The pins outputted at two places.
Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.
Note 3: THERMAL BALL must be connected to the ground (GND).
Table 1.4.2 Pin Assignments of the M32192F8xWG (1/4)
Port
Function 1
Function 2
DRI function
NBD function
Function
Type
State during
reset
State upon
exiting reset
A1
------
-
A2
VSS
-
VSS
-
VSS
-
A3
P220/CTX0/HACK#
P220 CTX0 (Note 1) HACK# (Note 1)
-Input/Output VCC-BUS
P220
Input
Hi-Z
During single-chip and
external extension modes
P45
Input
Hi-Z
During processor mode
CS1#
Output
Hi-Z
"H" level
A5
EXCVCC
-
EXCVCC
-
EXCVCC
-
A6
P150/TIN0/CLKOUT/WR#
P150
TIN0
CLKOUT (Note
1)
-
Input/Output VCC-BUS
P150
Input
Hi-Z
A7
P135/TIN21/RXD3
P135
TIN21
RXD3(Note1)
-Input/Output
VCCE
P135
Input
Hi-Z
A8
P131/TIN17/
PWMOFF1/DIN1
P131
TIN17/
PWMOFF1
-
DIN1
Input/Output
VCCE
P131
Input
Hi-Z
A9
MOD2
-
MOD2
-
VCCE
MOD2
-
A10
P126/TCLK2/CS2#/DD1
P126
TCLK2
CS2# (Note 1)
DD1 (Note 1) Input/Output
VCCE
P126
Input
Hi-Z
A11
P107/TO15/RXD4/DD0
P107
TO15
RXD4
DD0 (Note 1) Input/Output
VCCE
P107
Input
Hi-Z
A12
P103/TO11/TIN24
P103
TO11
TIN24
-
Input/Output
VCCE
P103
Input
Hi-Z
A13
JTDO/NBDEVNT# (Note 2)
-
JTDO
-
NBDEVNT#
Output
VCCE
JTDO
Output
Hi-Z
A14
JTMS (Note 2)
-JTMS
-
Input
VCCE
JTMS
Input
Hi-Z
A15
VSS
-
VSS
-
VSS
-
B1
XIN
-
XIN
-
Input
VCC-BUS
XIN
Input
-
B2
N.C.
-
B3
P221/CRX0/HREQ#
P221 CRX0 (Note 1) HREQ# (Note 1)
-Input
VCC-BUS
P221
Input
Hi-Z
During single-chip and
external extension modes
P46
Input
Hi-Z
During processor mode
A13
Output
Hi-Z
Undefined
B5
VSS
-
VSS
-
VSS
-
B6
P153/TIN3/WAIT#
P153
TIN3
WAIT# (Note 1)
-Input/Output VCC-BUS
P153
Input
Hi-Z
B7
P136/TIN22/CRX1
P136
TIN22
CRX1 (Note 1)
-Input/Output
VCCE
P136
Input
Hi-Z
B8
P132/TIN18/DIN2
P132
TIN18
-
DIN2
Input/Output
VCCE
P132
Input
Hi-Z
B9
N.C.
-
B10
N.C.
-
B11
P106/TO14/TXD4/DD1
P106
TO14
TXD4
DD1 (Note 1) Input/Output
VCCE
P106
Input
Hi-Z
B12
JTDI/NBDSYNC# (Note 2)
-
JTDI
-
NBDSYNC#
Input
VCCE
JTDI
Input
Hi-Z
B13
JTRST (Note 2)
-JTRST
-
Input
VCCE
JTRST
Input
Hi-Z
B14
P102/TO10/CTX0
P102
TO10
CTX0 (Note 1)
-Input/Output
VCCE
P102
Input
Hi-Z
B15
VDDE
-
VDDE
-
VDDE
-
C1
XOUT
-
XOUT
-
Input
VCC-BUS
XOUT
Output
XOUT
C2
N.C.
-
Input/Output
During single-chip and
external extension modes
P225
Input
Hi-Z
Input/Output
During processor mode
A12
Output
Hi-Z
Undefined
Input/Output
During single-chip and
external extension modes
P47
Input
Hi-Z
Input/Output
During processor mode
A14
Output
Hi-Z
Undefined
Input/Output
During single-chip mode
P43
Input
Hi-Z
Input/Output
During single-chip and
external extension modes
RD#
Output
Hi-Z
"H" level
Input/Output
During single-chip mode
P41
Input
Hi-Z
Input/Output
During single-chip and
external extension modes
BLW#/
BLE#
Output
Hi-Z
"H" level
C7
P137/TIN23/CTX1
P137
TIN23
CTX1 (Note 1)
-Input/Output
VCCE
P137
Input
Hi-Z
C8
P133/TIN19/DIN3
P133
TIN19
-
DIN3
Input/Output
VCCE
P133
Input
Hi-Z
C9
P127/TCLK3/CS3#/DD0
P127
TCLK3
CS3# (Note 1)
DD0 (Note 1) Input/Output
VCCE
P127
Input
Hi-Z
Input/Output
During single-chip and
external extension modes
P125
Input
Hi-Z
Input/Output
During processor mode
A10
Output
Hi-Z
C11
P105/TO13/
SCLKI4/SCLKO4/DD2
P105
TO13
SCLKI4/
SCLKO4
DD2 (Note 1) Input/Output
VCCE
P105
Input
Hi-Z
C12
VSS
-
VSS
-
VSS
-
C13
JTCK/NBDCLK (Note 2)
-
JTCK
-
NBDCLK
Input
VCCE
JTCK
Input
Hi-Z
C14
P101/TO9/CRX0
P101
TO9
CRX0 (Note 1)
-Input/Output
VCCE
P101
Input
Hi-Z
C15
P100/TO8
P100
TO8
-
Input/Output
VCCE
P100
Input
Hi-Z
Input/Output
During single-chip and
external extension modes
P224
Input
Hi-Z
Input/Output
During processor mode
A11
Output
Hi-Z
Undefined
D2
VSS
-
VSS
-
VSS
-
D3
VCC-BUS
-
VCC-BUS
-
VCC-BUS
-
Input/Output
During single-chip and
external extension modes
P44
Input
Hi-Z
Input/Output
During processor mode
CS0#
Output
Hi-Z
"H" level
Input/Output
During single-chip mode
P42
Input
Hi-Z
Input/Output
During single-chip and
external extension modes
BHW#/
BHE#
Output
Hi-Z
"H" level
D6
VCCE
-
VCCE
-
VCCE
-
D7
P134/TIN20/TXD3/DIN4
P134
TIN20
TXD3 (Note 1)
DIN4
Input/Output
VCCE
P134
Input
Hi-Z
D8
P130/TIN16/
PWMOFF0/DIN0
P130
TIN16/
PWMOFF0
-
DIN0
Input/Output
VCCE
P130
Input
Hi-Z
D9
N.C.
-
D10
N.C.
-
Input/Output
During single-chip and
external extension modes
P124
Input
Hi-Z
Input/Output
During processor mode
A9
Output
Hi-Z
D12
P104/TO12/TIN25/DD3
P104
TO12
TIN25
DD3 (Note 1) Input/Output
VCCE
P104
Input
Hi-Z
D13
P117/TO7/TO36/DD4
P117
TO7
TO36 (Note 1)
DD4 (Note 1) Input/Output
VCCE
P117
Input
Hi-Z
D14
P116/TO6/TO35/DD5
P116
TO6
TO35 (Note 1)
DD5 (Note 1) Input/Output
VCCE
P116
Input
Hi-Z
D15
P115/TO5/TO34/DD6
P115
TO5
TO34 (Note 1)
DD6 (Note 1) Input/Output
VCCE
P115
Input
Hi-Z
E1
N.C.
-
Input/Output
During single-chip and
external extension modes
P30
Input
Hi-Z
Input/Output
During processor mode
A15
Output
Hi-Z
Undefined
E3
VCCER
-
VCCER
-
Input/Output
-
VCCER
-
Input/Output
During single-chip and
external extension modes
P31
Input
Hi-Z
Input/Output
During processor mode
A16
Output
Hi-Z
Undefined
E5
THERMAL-BALL (Note 3)
-VSS
-
VSS
-
Pin No.
Symbol
Function
Type
Power
supply
Condition
Pin state when reset
A4
P45/CS1#/TIN9
P45
CS1#
TIN9
-
Input/Output VCC-BUS
B4
P46/A13/TIN10
P46
A13
TIN10
-
Input/Output VCC-BUS
CS3# (Note 1)
-
VCC-BUS
C3
P225/A12/CS3#
P225
A12
TIN11
-
VCC-BUS
C4
P47/A14/TIN11
P47
A14
-
VCC-BUS
C5
P43/RD#
P43
RD#
-
VCC-BUS
C6
P41/BLW#/BLE#
P41
BLW#/
BLE#
A10
DD2 (Note 1)
VCCE
C10
P125/TCLK1/A10/DD2
P125
TCLK1
CS2# (Note 1)
-
VCC-BUS
D1
P224/A11/CS2#
P224
A11
TIN8
-
VCC-BUS
D4
P44/CS0#/TIN8
P44
CS0#
-
VCC-BUS
D5
P42/BHW#/BHE#
P42
BHW#/
BHE#
A9
DD3 (Note 1)
VCCE
D11
P124/TCLK0/A9/DD3
P124
TCLK0
TIN4
DD16
VCC-BUS
E2
P30/A15/TIN4/DD16
P30
A15
TIN5
DD17
VCC-BUS
E4
P31/A16/TIN5/DD17
P31
A16