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10.3 TOP (Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS
10
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
10.3.2 Outline of Each Mode of TOP
Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected.
(1) Single-shot output mode
In single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" only once
and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
reload register, the counter is loaded with the content of “the reload register -1” and starts counting synchro-
nously with the count clock at the next circle. The counter counts down and stops.
The F/F output waveform in single-shot output mode is inverted at enable and upon underflow (F/F output
level is changed “L” to “H”, or “H” to “L”), generating a single-shot pulse waveform in width of “reload register
set value + 1” only once.
And also an interrupt request can be generated when the counter underflows. The counter value is “setting
value of reload register +1.”
(2) Delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of “reload register set value + 1”
after a finite time equal to “counter set value + 1” only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload register, it starts counting down from the counter’s set value synchronously with the
count clock.
The next cycle after first counter underflow, it is loaded with “the reload register value -1” and continues
counting down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted (F/F output level is changed “L” to
“H”, or “H” to “L”), when the counter underflows first time and next, generating a single-shot pulse waveform
in width of “reload register set value + 1” after a finite time equal to “first set value of counter + 1” only once.
And also an interrupt request can be generated when the counter underflows first time and next.
The effective counter value is “counter set value +1” or “reload register set value +1.”
(3) Continuous output mode
In continuous output mode, the timer counts down starting from the set value of the counter and at the cycle
after the counter underflows, it is loaded with the value that “ the reload register -1”. Thereafter, this opera-
tion is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is
inverted in width of “reload register set value + 1.”
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload register, it starts counting down from the counter’s set value synchronously with the
count clock and when the minimum count is reached, generates an underflow.
At the cycle after this underflow, the counter to be loaded with the content of “the reload register -1” and start
counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the
counter, disable count by writing to the enable bit in software.
The F/F output waveform in continuous output mode is inverted (F/F output level is changed “L” to “H”, or “H”
to “L”), at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops
counting. An interrupt request can be generated each time the counter underflows.
The effective counter value is “counter set value +1” and “reload register set value +1.”