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OVERVIEW
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
1.1 Outline of the 32192/32195/32196 Group
(3) Compact instruction code
The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the
16-bit instruction format especially helps to suppress the code size of a program.
Moreover, the availability of 32-bit instructions makes programming easier and provides higher per-
formance at the same clock speed than in architectures where the address space is segmented. For
example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or back-
ward from the currently executed address in one instruction, making programming easy.
1.1.2 Built-in Multiplier/Accumulator
(1) Built-in high-speed multiplier
The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to
execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods.
(2) DSP-comparable multiply-accumulate instructions
The M32R-FPU supports the following four types of multiply-accumulate instructions (or multiplication
instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator.
(1) 16 high-order bits of register × 16 high-order bits of register
(2) 16 low-order bits of register × 16 low-order bits of register
(3) All 32 bits of register × 16 high-order bits of register
(4) All 32 bits of register × 16 low-order bits of register
The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or
32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because
these instructions too are executed in one CPUCLK period, when used in combination with high-
speed data transfer instructions such as Load & Address Update or Store & Address Update, they
enable the M32R-FPU to exhibit superior data processing capability comparable to that of a DSP.
1.1.3 Built-in Single-precision FPU
The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754
standards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Divi-
sion by Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round
toward 0, round toward + Infinity and round toward – Infinity) are supported. What’s more, because
general-purpose registers are used to perform floating-point arithmetic, the overhead associated
with transferring the operand data can be reduced.
1.1.4 Built-in Flash Memory and RAM
The 32192/32195/32196 contains a RAM that can be accessed with zero wait state, allowing to
design a high-speed embedded system.
The internal flash memory can be written to while mounted on a printed circuit board (on-board
writing). Use of flash memory facilitates development work, because the chip used at the develop-
ment stage can be used directly in mass-production, allowing for a smooth transition from prototype
to mass-production without the need to change the printed circuit board.
The internal flash memory can be rewritten as many as 100 times.