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32192/32195/32196 Group Hardware Manual
OVERVIEW
Rev.1.10 REJ09B0123-0110 Apr.06.07
1.1 Outline of the 32192/32195/32196 Group
The 32192/32195/32196 Group (hereinafter simply the 32192/32195/32196) belongs to the M32R/ECU Series
in the M32R Family of Renesas microcomputers. For details about the current development status of the
32192/32195/32196, please contact your nearest office of Renesas or its distributor.
Table 1.1.1 Product List
Type Name
ROM
RAM
Frequency
Power supply voltage
Temperature Range
capacity
at single-supply
at double-supply
(Note 1)
M32192F8VFP
1 Mbytes
176 Kbytes
128 MHz
3.3V
5V, 3.3V
–40°C to 125°C
M32192F8UFP
1 Mbytes
176 Kbytes
160 MHz
3.3V
5V, 3.3V
–40°C to 105°C
M32192F8TFP
1 Mbytes
176 Kbytes
160 MHz
5V or 3.3V
5V, 3.3V
–40°C to 85°C
M32192F8VWG
1 Mbytes
176 Kbytes
128 MHz
3.3V
5V, 3.3V
–40°C to 125°C
M32192F8UWG
1 Mbytes
176 Kbytes
160 MHz
3.3V
5V, 3.3V
–40°C to 105°C
M32192F8TWG
1 Mbytes
176 Kbytes
160 MHz
5V or 3.3V
5V, 3.3V
–40°C to 85°C
M32195F4VFP
512 Kbytes
32 Kbytes
128 MHz
3.3V
5V, 3.3V
–40°C to 125°C
M32195F4UFP
512 Kbytes
32 Kbytes
160 MHz
3.3V
5V, 3.3V
–40°C to 105°C
M32195F4TFP
512 Kbytes
32 Kbytes
160 MHz
5V or 3.3V
5V, 3.3V
–40°C to 85°C
M32196F8VFP
1 Mbytes
64 Kbytes
128 MHz
3.3V
5V, 3.3V
–40°C to 125°C
M32196F8UFP
1 Mbytes
64 Kbytes
160 MHz
3.3V
5V, 3.3V
–40°C to 105°C
M32196F8TFP
1 Mbytes
64 Kbytes
160 MHz
5V or 3.3V
5V, 3.3V
–40°C to 85°C
Note 1: This does not guarantee continuous operation and there is a limitation on the length of use (temperature profile).
1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU)
(1) Based on a RISC architecture
The 32192/32195/32196 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in
this group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order
to materialize the common instruction set and the high-precision arithmetic operation of the M32R
CPU. The 32192/32195/32196 products listed in the above table are built around the M32R-FPU
and incorporates flash memory, RAM and various peripheral functions, all integrated into a single
chip.
The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store instruc-
tions, and various arithmetic/logic operations are executed using register-to-register operation instructions.
The M32R-FPU internally contains sixteen 32-bit general-purpose registers. The instruction set con-
sists of 100 discrete instructions in total (83 instructions common to the M32R Family plus 17 FPU
and extended instructions). These instructions are either 16 bits or 32 bits long.
In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions such as
Load & Address Update and Store & Address Update. These instructions help to speed up data transfers.
(2) Six-stage pipelined processing
The M32R-FPU supports six-stage pipelined instruction processing. Not just load/store instructions
and register-to-register operation instructions, but also floating-point arithmetic instructions and
compound instructions such as Load & Address Update and Store & Address Update are executed
in one CPUCLK period (which is equivalent to 6.25 ns when f(CPUCLK) = 160 MHz).
Although instructions are supplied to the execution stage in the order in which they were fetched, it
is possible that if the load/store instruction supplied first is extended by wait cycles inserted in
memory access, the subsequent register-to-register operation instruction will be executed before
that instruction. Using such a facility, which is known as the “out-of-order-completion” mechanism,
the M32R-FPU is able to control instruction execution without wasting clock cycles.
1.1 Outline of the 32192/32195/32196 Group