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32192/32195/32196 Group Hardware Manual
OVERVIEW
Rev.1.10 REJ09B0123-0110 Apr.06.07
Table 1.2.1 Features of the 32192/32195/32196 (2/3)
1.2 Block Diagram
Functional Block
Features
A/D Converter (ADC)
16 channels: 10-bit resolution A/D converter × 1 block
Conversion modes: In addition to ordinary A/D conversion mode, comparator mode and
2-channel simultaneous sampling mode.
Operation modes: Single conversion mode and n-channel scan mode (n = 1–16)
Sample-and-hold function: Performs A/D conversion with the analog input voltages sampled at
start of A/D conversion.
A/D disconnection detection assist function: Suppresses effects of the analog input voltage
leakage from the preceding channel during A/D conversion.
An inflow current bypass circuit is built-in.
Can generate an interrupt or start DMA transfer upon completion of A/D conversion.
Either 8-bit or 10-bit conversion results can be read out.
Interrupt request: Completion of A/D conversion
DMA transfer request: Completion of A/D conversion
Serial Interface (SIO)
6-channel serial interface
Can be chosen to be clock-synchronous serial interface or clock-asynchronous serial interface.
Data can be transferred at high speed (5 Mbits per second during clock-synchronous mode or
2.5 Mbits per second during clock-asynchronous mode when f(BCLK) = 40 MHz).
Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed
DMA transfer request: Reception completed or transmit buffer empty
CAN
32 message slots × 2 blocks
Compliant with CAN specification 2.0B active.
Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off
or single shot
DMA transfer request: Failed to send, transmission completed or reception completed
Real-Time Debugger
Internal RAM can be rewritten or monitored independently of the CPU by entering a command
(RTD)
from the outside.
Comes with exclusive clock-synchronous serial ports.
Interrupt request: RTD interrupt command input
Non-Break Debug
Can access to all resources on the address map from the outside
(NBD)
Clock-synchronous parallel interface (4-bit)
Event output function
RAM monitor function
Direct RAM Interface
Can control capture of clock-synchronous parallel data to the internal RAM independently of the CPU
(DRI)
Clock-synchronous parallel input (8-bit, 16-bit or 32-bit)
Maximum transfer rate: 40 Mbytes/s (when f(CPUCLK)=160 MHz)
Interrupt Controller (ICU)
Controls interrupt requests from the internal peripheral I/O.
Supports 8-level interrupt priority including an interrupt disabled state.
External interrupt: 27 sources (SBI#, TIN0, TIN3–TIN11, TIN16–TIN27, TIN30–TIN33)
TIN pin input sensing: Rising, falling or both edges or “H” or “L” level
Wait Controller
Controls wait states for access to the external extension area.
Insertion of 0–15 wait states by setting up in software + wait state extension by entering WAIT# signal
PLL
A multiply-by-8 clock generating circuit
Clock
Maximum external input clock frequency (XIN) is 20.0 MHz. (Note 1)
CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM
The maximum CPU clock is 160 MHz (when f(XIN) = 20 MHz).
BCLK: Operating clock for the internal peripheral I/O and external data bus
The maximum peripheral clock is 40 MHz (peripheral module access when f(XIN) = 20 MHz).
BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin.
CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin.