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參數(shù)資料
| 型號(hào)： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 70/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
CIRCUIT LAYOUT INFORMATION
The PCB layout is critical in achieving good image quality from
the AD9992. All of the supply pins, particularly the AVDD,
TCVDD, RGVDD, and HVDD supplies, must be decoupled to
ground with good quality high frequency chip capacitors. The
decoupling capacitors should be located as close as possible to
the supply pins and should have a very low impedance path to a
continuous ground plane. If possible, there should be a 4.7 μF
or larger value bypass capacitor for each main supply—AVDD,
HVDD, and DRVDD—although this is not necessary for each
individual pin. In most applications, the supply for RGVDD
and HVDD is shared, which can be done as long as the
individual supply pins are separately bypassed with 0.1 μF
capacitors. A separate 3 V supply can also be used for DRVDD,
but this supply pin should still be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is not
recommended.
Rev. 0 | Page 70 of 92
The analog bypass pins (REFT and REFB) should be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should be located close to
the pin.
The H1 to H8, HL, and RG traces should be designed to have
low inductance to minimize distortion of the signals. The
complementary signals, H1/H3/H5/H7 and H2/H4/H6/H8,
should be routed as close together and as symmetrically as
possible to minimize mutual inductance. Heavier PCB traces
are recommended because of the large transient current
demand on H1 to H8 by the CCD. If possible, physically
locating the AD9992 closer to the CCD reduces the inductance
on these lines. As always, the routing path should be as direct as
possible from the AD9992 to the CCD.
Note that it is recommended that all H1 to H8 outputs on the
AD9992 be used together for maximum flexibility in drive
strength settings. A typical CCD with H1 and H2 inputs only
should have the AD9992’s H1, H3, H5, and H7 outputs connected
together to drive the CCD’s H1, and H2, H4, H6, and H8 outputs
connected together to drive the CCD’s H2. Similarly, a CCD
with H1, H2, H3, and H4 inputs should have the following:
H1 and H3 connected to the CCD’s H1.
H2 and H4 connected to the CCD’s H2.
H5 and H7 connected to the CCD’s H3.
H6 and H8 connected to the CCD’s H4.
Typical 3 V System
The AD9992 typical circuit connections for a 3 V system are
shown in Figure 79. This application uses an external 3.3 V
supply, which is connected to the AD9992’s LDO input. The
LDO is configured to output 1.8 V for the AD9992’s core supply
by connecting the LDO1P8EN pin to 3.3 V and the LDO3P2EN
pin to ground. The LDOOUT and SENSE pins are shorted
together and used to supply 1.8 V to the AVDD, TCVDD, and
DVDD pins.
Typical 1.8 V System
The internal LDO can be disabled by tying the LDO pins to
ground (LDOIN, LDO1P8EN, LDO3P2EN, LDOOUT, and
SENSE). In this case, an external 1.8 V regulator is required to
supply 1.8 V to the AVDD, TCVDD, and DVDD pins.
All of the AD9992’s remaining supplies can be directly supplied
with 1.8 V. The internal charge pump (CP) can be used to
generate 3.3 V for the H and RG supplies.
The AD9992 typical circuit connections for a 1.8 V system are
shown in Figure 80.
External Crystal Application
The AD9992 contains an on-chip oscillator for driving an
external crystal. Figure 81 shows an example application using a
typical 27 MHz crystal. For the exact values of the external
resistors and capacitors, it is best to consult the crystal
manufacturer’s data sheet.
Note that a 2× crystal is not recommended for use with the
CLO oscillator circuit. The crystal frequency should not exceed
40 MHz.
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
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