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參數(shù)資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 20/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 23 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions are used to designate the start and
stop positions of the blanking period. Additionally, there are
separate masking polarity controls for H1, H2, and HL that
designate the polarity of the horizontal clock signals during the
blanking period. Setting HBLKMASK_H1 high sets H1, and
therefore H3, H5, and H7, low during the blanking, as shown in
Figure 24. As with the CLPOB and PBLK signals, HBLK
registers are available in each V-sequence, allowing different
blanking signals to be used with different vertical timing
sequences.
Rev. 0 | Page 20 of 92
The AD9992 supports three modes of HBLK operation. HBLK
Mode 0 supports basic operation and some support for special
HBLK patterns. HBLK Mode 1 supports pixel mixing HBLK
operation. HBLK Mode 2 supports advanced HBLK operation.
The following sections describe each mode in detail. Register
parameters are described in detail in Table 10.
HBLK Mode 0 Operation
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the
standard HBLK interval. However, the additional toggle
positions can be used to generate special HBLK patterns, as
shown in Figure 25. The pattern in this example uses all six
toggle positions to generate two extra groups of pulses during
the HBLK interval. By changing the toggle positions, different
patterns can be created.
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
HD
HBLK
BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0)
BLANK
BLANK
HBLKTOGE1
HBLKTOGE2
0
Figure 23. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0)
HD
HBLK
H1/H3/H5/H7
H1/H3/H5/H7
H2/H4/H6/H8
THE POLARITY OF H1/H3/H5/H7 DURING BLANKING IS PROGRAMMABLE
(H2/H4/H6/H8 AND HL ARE SEPARATELY PROGRAMMABLE)
0
Figure 24. HBLK Masking Polarity Control
HBLK
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0)
Figure 25. Using Multiple Toggle Positions for HBLK (HBLKMODE = 0)
H1/H3
H2/H4
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
0
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
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