參數(shù)資料
型號(hào)： AD9992BBCZRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 12-Bit CCD Signal Processor with Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝： 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁數(shù)： 35/92頁
文件大?。?/td> 718K
代理商： AD9992BBCZRL
AD9992
Using the LASTREPLEN_EN
The LASTREPLEN_EN register (Address 0x00, Bits [19:16] in
the sequence registers) is used to enable a separate pattern
length to be used in the final repetition of several pulse
repetitions. It is recommended that the LASTREPLEN_EN
register bits be set high (enabled) and the LASTREPLEN_A,
LASTREPLEN_B, LASTREPLEN_C, and LASTREPLEN_D
registers be set to a value equal to the VLENA, VLENB,
VLENC, and VLEND register values, respectively.
Rev. 0 | Page 35 of 92
Generating Line Alternation for V-Sequences and HBLK
During low resolution readout, some CCDs require a different
number of vertical clocks on alternate lines. The AD9992 can
support this by using the VREP registers. This allows a different
number of V-pattern group repetitions to be programmed on
odd and even lines. Only the number of repeats can be different
in odd and even lines, while the V-pattern group remains the
same. There are separate controls for the assigned Group A,
Group B, Group C, and Group D patterns. All groups can
support odd and even line alternation. Group A uses the
VREPA_1 and VREPA_2 registers; Group B, Group C, and
Group D use the corresponding VREP_ODD and VREP_EVEN
registers. With the additional VREPA_3 and VREPA_4
registers, Group A can also support 3-line and 4-line
alternation.
As discussed in the Generating HBLK Line Alternation section,
the HBLK signal can be alternated for odd and even lines.
Figure 41 shows an example of V-pattern group repetition
alternation and HBLK Mode 0 alternation used together.
V1
V2
V24
HD
HBLK
TOGE1
TOGE2
TOGO1
TOGO2
TOGE1
TOGE2
NOTES
1. THE NUMBER OF REPEATS FOR V-PATTERN GROUPS A/B/C/D CAN BE ALTERNATED ON ODD AND EVEN LINES.
2. GROUP A ALSO SUPPORTS 3- AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.
3. THE HBLK TOGGLE POSITIONS CAN BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS.
VREPA_1 = 2
(OR VREPB/C/D_EVEN = 2)
VREPA_2 = 5
(OR VREPB/C/D_ODD = 5)
VREPA_1 = 2
(OR VREPB/C/D_EVEN = 2)
0
Figure 41. Odd/Even Line Alternation of V-Pattern Group Repetitions and HBLK Toggle Positions
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參數(shù)描述
AD9993BBCZ 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1
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